> On Dec 17, 2014, at 12:26 PM, Frank Zerangue <[email protected]> wrote: > > I have a private port for an iMX31 based board which is itself based on > evbarm. When I enable L2 cache in start.S the startup process freezes when I > switch to the real L1 page table in initarm().
Don't do it that way. Make sure the arml2cc config line has no flags or flags 0 and it will enable the cache when it gets attached if it's not already enabled. > I wrote a custom flash boot program that loads the kernel with an initial ram > disk. I enable L2 cache in the flash boot program and I see about a 15% to > 20% improvement in load time; but when I start the kernel I do not enable L2 > cache for the reason described above. > > Can you give me some clues into the infrastructure that may need work to > support L2 cache? The above is all that needs to be done on cortex-a9.
