Additional comments:
0. I am not looking at the layout with Altium but with another program,
so I may be mistaken here, but it appears that the Gerber files for the
Power_Plane were generated without the actual plane data for the
islands(I assume those are positive planes) - just with the contour
lines of the plane region. See for example missing FPGA 1.0V plane data
on inner layer #4 in the Gerber file set.
1. Under the analog noise circuitry you do keep out the GND on inner
layer #1 (a good thing), but no keep-out there for GND on inner layer #6
nor for the power planes.
2. I guess that supposedly there are 4 mechanical mounting holes at the
4 corners of the board. However, only the bottom two are proper holes.
The top 2 are not.
3. Most of the large vias that come out of the decoupling capacitors are
too close to comfort to the capacitor pads. In many cases the clearance
between the soldermask of the decap pad and the via hole is 4 mil
(0.1mm) - a border line case that with the slightest manufacturing
deviation will render the gap w/o solder mask (not a good thing).
4. Via on U8's pad should be moved away. See attached pic.
5. I suggest to fill in with GND/PWR planes the large empty areas in
inner layers - good for electrical performance and for etching
uniformity in the mfg. process.
6. A nit: The FPGA JTAG table nomenclature is rotated 180 deg from other
text on board.
Jacob
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