Hi Jason, Great that you're interested in helping out!
Jason van Aardt wrote: > Using the Gigabit Serdes on the Artix, it would be possible to > include two Gigabit ethernet ports One conscious design decision of Cryptech HDL is to remain hardware agnostic as long as there isn't a VERY good reason to use specific hardware. The HDL is supposed to also be maximally useful for other FPGAs, as well as ASIC processes. > and use the device as a bump in the wire for a L2/L3 encrypter. That said, adding GbE or PCIe (Pavel: host drivers aren't bad) can certainly be worthwhile, indeed the server use case would benefit from a PCIe interface, but remember that the current FPGA is inside of a trust boundary which the host is not allowed to access. The trust boundary edge currently resides within the STM32, whose host-facing interface is the (intentionally stupidly trivial) UART. Replacing that host interface means replacing the STM32 with a different FMC master, e.g. a second FPGA. //Peter _______________________________________________ Tech mailing list Tech@cryptech.is https://lists.cryptech.is/listinfo/tech
