of possible background interest wrt FPGAs...
Subject: [netseminar] Stanford Platform Lab Seminar, *Tuesday FEB / 28* @ 4:30pm, Raghu Prabhakar (Stanford University) From: Alex Pinedo <asan...@cs.stanford.edu> Date: Thu, 23 Feb 2017 11:49:10 -0800 To: platform...@lists.stanford.edu, netsemi...@lists.stanford.edu, christos_stude...@mailman.stanford.edu, "ON.Lab All" <a...@onlab.us>, cs-semin...@lists.stanford.edu Cc: "Pinedo, Alex Sandra" <apin...@stanford.edu> *Speaker: *Raghu Prabhakar, Stanford University *Title:* Automatic Generation of Efficient Accelerator Designs for Reconfigurable Hardware *Abstract: * Acceleration in the form of customized datapaths offers large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators. However, current tools for targeting FPGAs offer inadequate support for high-level programming, resource estimation, and rapid and automatic design space exploration. In this talk, I will describe a design framework we have developed that addresses these challenges. We introduce a new parallel patterns-based representation of hardware using parameterized templates that capture locality and parallelism information at multiple levels of nesting. We describe an area estimation technique using high-level models to account for low-level effects from hardware place-and-route tools. We use our estimation capabilities to rapidly explore a large space of designs across tile sizes, parallelization factors, and optional coarse-grained pipelining, all at multiple loop levels. We show that estimates average 4.8% error for logic resources, 6.1% error for runtimes, and are 279 to 6533 times faster than a commercial high-level synthesis tool. We compare the best-performing designs to optimized CPU code running on a server-grade 6 core processor and show speedups of up to 16.7× *About the speaker*: Raghu Prabhakar is a fourth-year PhD candidate in the Computer Science department at Stanford University, co-advised by Prof. Christos Kozyrakis and Prof. Kunle Olukotun. He is interested in exploring new programming models, compiler techniques, and architectures for spatially reconfigurable hardware. _______________________________________________ Tech mailing list Tech@cryptech.is https://lists.cryptech.is/listinfo/tech
