On Wed, 13 Jun 2018 12:55:50 -0400, Michael wrote: ... > It kind of feels to me like there is a bottleneck somewhere else > that is not dependent on sclk
Until proven otherwise, my strong suspicion is that the bottleneck is the poll-and-spin-wait for every 32-bit word transferred in either direction on the FMC bus. We're doing the tests (100MHz first, FMC bus sync at 90MHz second) in this order because (a) the work was already and (b) we want the timing data in any case, both for its own sake and as a control experiment for comparison with the FMC sync case. But at this point I would have been more surprised if you had seen a dramatic improvement. _______________________________________________ Tech mailing list Tech@cryptech.is https://lists.cryptech.is/listinfo/tech
