Well, try as I might, I can't get the design to build with ModExpNG at
180MHz. It consistently fails with 2 timing errors on
TS_clkmgr_mmcm_inst_mmcm_clkout2 (the 180MHz clock line). I sent Pavel
the timing report last week, but I've attached it here in case anyone
else has some other insight.
OTOH, cutting ModExpNG back to 90MHz, I was able to build and test.
Overall it ran faster than the previous test, because cores were clocked
at 90MHz vs 60MHz.
The only place it ran slower was in hal_ks_fetch, because the FMC bus is
now clocked at 45MHz vs. 60MHz previously, and hal_aes_keyunwrap spends
most of its time sending data back and forth over the FMC bus. This may
be a good time to integrate Joachim's keywrap core into the mainline.
modexpa7 modexpng
hal_rpc_pkey_sign 104.947 79.515
hal_ks_fetch 19.089 19.089
pkey_local_sign_rsa 85.778 60.344
hal_rsa_decrypt 85.078 59.641
rsa_crt 81.328 55.897
modexp2/ng 55.007 44.409
hal_modexp2/ng 44.497 17.557
I don't understand why the FMC bus can't be clocked at 90MHz, since
that's its documented max.
Alternately, is it possible to clock the cores at 120MHz, and FMC at
60MHz? I remember we did some work on the cores at some point, but I'm
really not the FPGA guy.
paul
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -e 10
alpha_fmc_hsm_ng_par.ncd alpha_fmc_hsm_ng.pcf -o alpha_fmc_hsm_ng_err.twr
Design file: alpha_fmc_hsm_ng_par.ncd
Physical constraint file: alpha_fmc_hsm_ng.pcf
Device,package,speed: xc7a200t,fbg484,C,-1 (PRODUCTION 1.10 2013-10-13)
Report level: error report, limited to 10 items per constraint
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
32 logic loops found and disabled.
----------------------------------------------------------------------
! Warning: The following connections close logic loops, and some paths !
! through these connections may not be analyzed. To better !
! understand the logic associated with these loops, run a !
! Analyze Against User-Defined End-Point Analysis inside !
! Timing Analyzer (timingan) with the listed signal as a !
! source NET (*signal_name). The Timing Report will display !
! all the paths associated with this signal and the logic !
! loop will be reported. !
! !
! Signal Driver Load !
! -------------------------------- ---------------- ---------------- !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X134Y84.BMUX SLICE_X134Y84.B2 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X134Y84.B SLICE_X134Y84.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X134Y84.DMUX SLICE_X134Y84.D2 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X134Y84.D SLICE_X134Y84.D5 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X137Y84.CMUX SLICE_X137Y84.C1 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X137Y84.C SLICE_X137Y84.C4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X137Y85.BMUX SLICE_X137Y85.B1 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X137Y85.B SLICE_X137Y85.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X137Y85.DMUX SLICE_X137Y85.D3 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X137Y85.D SLICE_X137Y85.D5 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X137Y88.BMUX SLICE_X137Y88.B5 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X137Y88.B SLICE_X137Y88.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X137Y88.DMUX SLICE_X137Y88.D3 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X137Y88.D SLICE_X137Y88.D1 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X137Y90.BMUX SLICE_X137Y90.B1 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X137Y90.B SLICE_X137Y90.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X136Y84.BMUX SLICE_X136Y84.B3 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X136Y84.B SLICE_X136Y84.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X136Y84.DMUX SLICE_X136Y84.D2 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X136Y84.D SLICE_X136Y84.D5 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X136Y87.BMUX SLICE_X136Y87.B3 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X136Y87.B SLICE_X136Y87.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X136Y89.BMUX SLICE_X136Y89.B1 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X136Y89.B SLICE_X136Y89.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X139Y87.BMUX SLICE_X139Y87.B5 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X139Y87.B SLICE_X139Y87.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X139Y89.BMUX SLICE_X139Y89.B1 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X139Y89.B SLICE_X139Y89.B4 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X140Y87.BMUX SLICE_X140Y87.B2 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X140Y87.B SLICE_X140Y87.B1 !
! ay/Madd_adder_osc.sum_Madd_cy<0> ICE_X141Y85.BMUX SLICE_X141Y85.B5 !
! ay/Madd_adder_osc.sum_Madd_cy<0> SLICE_X141Y85.B SLICE_X141Y85.B4 !
----------------------------------------------------------------------
================================================================================
Timing constraint: TS_fmc_clk = PERIOD TIMEGRP "TNM_fmc_clk" 22.222 ns HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 10.000ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clkmgr_mmcm_inst_mmcm_clkout0 = PERIOD TIMEGRP
"clkmgr_mmcm_inst_mmcm_clkout0" TS_fmc_clk / 2 PHASE -2.77775 ns HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
17285700 paths analyzed, 200966 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component
switching limit errors)
Minimum period is 11.098ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_core_selector = MAXDELAY FROM TIMEGRP
"TNM_CORE_SELECTOR_MUX_SRC" TO TIMEGRP "TNM_CORE_SELECTOR_MUX_DST"
TS_clkmgr_mmcm_inst_mmcm_clkout0 * 2;
For more information, see From:To (Multicycle) Analysis in the Timing Closure
User Guide (UG612).
4158 paths analyzed, 224 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 7.935ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clkmgr_mmcm_inst_mmcm_clkout1 = PERIOD TIMEGRP
"clkmgr_mmcm_inst_mmcm_clkout1" TS_fmc_clk PHASE -2.77775 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
188 paths analyzed, 124 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component
switching limit errors)
Minimum period is 13.218ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clkmgr_mmcm_inst_mmcm_clkout2 = PERIOD TIMEGRP
"clkmgr_mmcm_inst_mmcm_clkout2" TS_fmc_clk / 4 PHASE -2.77775 ns HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide
(UG612).
81931 paths analyzed, 32114 endpoints analyzed, 2 failing endpoints
2 timing errors detected. (2 setup errors, 0 hold errors, 0 component
switching limit errors)
Minimum period is 5.588ns.
--------------------------------------------------------------------------------
Slack: -0.033ns (requirement - (data path - clock path skew +
uncertainty))
Source: cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
(FF)
Destination:
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
(FF)
Requirement: 5.555ns
Data Path Delay: 5.456ns (Levels of Logic = 6)
Clock Path Skew: -0.090ns (1.389 - 1.479)
Source Clock: core_clk rising at -2.777ns
Destination Clock: core_clk rising at 2.778ns
Clock Uncertainty: 0.042ns
Clock Uncertainty: 0.042ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.045ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner:
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24 to
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X82Y192.DQ Tcko 0.456
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
SLICE_X82Y192.A5 net (fanout=7) 0.646
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
SLICE_X82Y192.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd23-In1
SLICE_X87Y189.B3 net (fanout=4) 0.871
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[5]_GND_117_o_equal_19_o
SLICE_X87Y189.B Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]_SW0
SLICE_X87Y189.A4 net (fanout=1) 0.433 cores/N2556
SLICE_X87Y189.A Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]
SLICE_X87Y188.B2 net (fanout=6) 0.829
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[1]
SLICE_X87Y188.B Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/out11
SLICE_X91Y187.A4 net (fanout=3) 0.850
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
SLICE_X91Y187.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_valid_lsb_adv_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.D3 net (fanout=5) 0.706
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.CLK Tas 0.045
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_118_o1
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
-------------------------------------------------
---------------------------
Total 5.456ns (1.121ns logic, 4.335ns
route)
(20.5% logic, 79.5%
route)
--------------------------------------------------------------------------------
Slack: -0.024ns (requirement - (data path - clock path skew +
uncertainty))
Source: cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10
(FF)
Destination:
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
(FF)
Requirement: 5.555ns
Data Path Delay: 5.510ns (Levels of Logic = 6)
Clock Path Skew: -0.027ns (0.819 - 0.846)
Source Clock: core_clk rising at -2.777ns
Destination Clock: core_clk rising at 2.778ns
Clock Uncertainty: 0.042ns
Clock Uncertainty: 0.042ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.045ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner:
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10 to
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y191.BQ Tcko 0.456
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd1
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10
SLICE_X87Y191.B2 net (fanout=9) 0.717
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10
SLICE_X87Y191.BMUX Tilo 0.360
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd1
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd9-In1
SLICE_X87Y189.B5 net (fanout=7) 0.618
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[5]_GND_117_o_equal_21_o
SLICE_X87Y189.B Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]_SW0
SLICE_X87Y189.A4 net (fanout=1) 0.433 cores/N2556
SLICE_X87Y189.A Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]
SLICE_X87Y188.B2 net (fanout=6) 0.829
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[1]
SLICE_X87Y188.B Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/out11
SLICE_X91Y187.A4 net (fanout=3) 0.850
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
SLICE_X91Y187.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_valid_lsb_adv_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.D3 net (fanout=5) 0.706
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.CLK Tas 0.045
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_118_o1
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
-------------------------------------------------
---------------------------
Total 5.510ns (1.357ns logic, 4.153ns
route)
(24.6% logic, 75.4%
route)
--------------------------------------------------------------------------------
Slack: -0.020ns (requirement - (data path - clock path skew +
uncertainty))
Source: cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
(FF)
Destination:
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_7
(FF)
Requirement: 5.555ns
Data Path Delay: 5.443ns (Levels of Logic = 6)
Clock Path Skew: -0.090ns (1.389 - 1.479)
Source Clock: core_clk rising at -2.777ns
Destination Clock: core_clk rising at 2.778ns
Clock Uncertainty: 0.042ns
Clock Uncertainty: 0.042ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.045ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner:
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24 to
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X82Y192.DQ Tcko 0.456
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
SLICE_X82Y192.A5 net (fanout=7) 0.646
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
SLICE_X82Y192.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd23-In1
SLICE_X87Y189.B3 net (fanout=4) 0.871
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[5]_GND_117_o_equal_19_o
SLICE_X87Y189.B Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]_SW0
SLICE_X87Y189.A4 net (fanout=1) 0.433 cores/N2556
SLICE_X87Y189.A Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]
SLICE_X87Y188.B2 net (fanout=6) 0.829
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[1]
SLICE_X87Y188.B Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/out11
SLICE_X91Y187.A4 net (fanout=3) 0.850
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
SLICE_X91Y187.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_valid_lsb_adv_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.D3 net (fanout=5) 0.706
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.CLK Tas 0.032
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o2
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_7
-------------------------------------------------
---------------------------
Total 5.443ns (1.108ns logic, 4.335ns
route)
(20.4% logic, 79.6%
route)
--------------------------------------------------------------------------------
Slack: -0.011ns (requirement - (data path - clock path skew +
uncertainty))
Source: cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10
(FF)
Destination:
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_7
(FF)
Requirement: 5.555ns
Data Path Delay: 5.497ns (Levels of Logic = 6)
Clock Path Skew: -0.027ns (0.819 - 0.846)
Source Clock: core_clk rising at -2.777ns
Destination Clock: core_clk rising at 2.778ns
Clock Uncertainty: 0.042ns
Clock Uncertainty: 0.042ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.045ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner:
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10 to
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y191.BQ Tcko 0.456
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd1
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10
SLICE_X87Y191.B2 net (fanout=9) 0.717
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd10
SLICE_X87Y191.BMUX Tilo 0.360
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd1
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd9-In1
SLICE_X87Y189.B5 net (fanout=7) 0.618
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[5]_GND_117_o_equal_21_o
SLICE_X87Y189.B Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]_SW0
SLICE_X87Y189.A4 net (fanout=1) 0.433 cores/N2556
SLICE_X87Y189.A Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]
SLICE_X87Y188.B2 net (fanout=6) 0.829
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[1]
SLICE_X87Y188.B Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/out11
SLICE_X91Y187.A4 net (fanout=3) 0.850
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
SLICE_X91Y187.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_valid_lsb_adv_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.D3 net (fanout=5) 0.706
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.CLK Tas 0.032
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o2
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_7
-------------------------------------------------
---------------------------
Total 5.497ns (1.344ns logic, 4.153ns
route)
(24.4% logic, 75.6%
route)
--------------------------------------------------------------------------------
Slack: -0.010ns (requirement - (data path - clock path skew +
uncertainty))
Source: cores/modexpng_inst/modexpng/uop_engine/mmm_ena_y_r (FF)
Destination:
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
(FF)
Requirement: 5.555ns
Data Path Delay: 5.433ns (Levels of Logic = 6)
Clock Path Skew: -0.090ns (1.389 - 1.479)
Source Clock: core_clk rising at -2.777ns
Destination Clock: core_clk rising at 2.778ns
Clock Uncertainty: 0.042ns
Clock Uncertainty: 0.042ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.045ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner:
cores/modexpng_inst/modexpng/uop_engine/mmm_ena_y_r to
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X83Y191.DMUX Tshcko 0.594
cores/modexpng_inst/modexpng/reductor_y/busy_now_shreg<4>
cores/modexpng_inst/modexpng/uop_engine/mmm_ena_y_r
SLICE_X82Y192.A6 net (fanout=7) 0.485
cores/modexpng_inst/modexpng/uop_engine/mmm_ena_y_r
SLICE_X82Y192.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd24
cores/modexpng_inst/modexpng/mmm_y/fsm_state_FSM_FFd23-In1
SLICE_X87Y189.B3 net (fanout=4) 0.871
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[5]_GND_117_o_equal_19_o
SLICE_X87Y189.B Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]_SW0
SLICE_X87Y189.A4 net (fanout=1) 0.433 cores/N2556
SLICE_X87Y189.A Tilo 0.124 cores/N2556
cores/modexpng_inst/modexpng/mmm_y/fsm_state_fsm_state_next[1]
SLICE_X87Y188.B2 net (fanout=6) 0.829
cores/modexpng_inst/modexpng/mmm_y/fsm_state_next[1]
SLICE_X87Y188.B Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/out11
SLICE_X91Y187.A4 net (fanout=3) 0.850
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_reduce_or_108_o
SLICE_X91Y187.A Tilo 0.124
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_valid_lsb_adv_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.D3 net (fanout=5) 0.706
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_114_o1
SLICE_X90Y187.CLK Tas 0.045
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/fsm_state_next[5]_GND_123_o_Select_118_o1
cores/modexpng_inst/modexpng/mmm_y/recombinator_block/xy_bitmap_lsb_adv<6>_6
-------------------------------------------------
---------------------------
Total 5.433ns (1.259ns logic, 4.174ns
route)
(23.2% logic, 76.8%
route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "TNM_FMC_IN_DATA" OFFSET = IN 7.5 ns VALID 17.5 ns
BEFORE COMP "fmc_clk" "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide
(UG612).
32 paths analyzed, 32 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 6.042ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "TNM_FMC_IN_ADDR" OFFSET = IN 10 ns VALID 9 ns
BEFORE COMP "fmc_clk" "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide
(UG612).
24 paths analyzed, 24 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 9.454ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "TNM_FMC_IN_CONTROL" OFFSET = IN 9.5 ns VALID 13.5
ns BEFORE COMP "fmc_clk" "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide
(UG612).
3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 7.459ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 6 ns BEFORE COMP
"fmc_clk" "FALLING";
For more information, see Offset Out Analysis in the Timing Closure User Guide
(UG612).
32 paths analyzed, 32 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
Maximum allowable offset is 21.951ns.
--------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_fmc_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period |
Timing Errors | Paths Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative |
Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_fmc_clk | 22.222ns| 10.000ns| 22.352ns|
0| 2| 0| 17371977|
| TS_clkmgr_mmcm_inst_mmcm_clkou| 11.111ns| 11.098ns| 3.968ns|
0| 0| 17285700| 4158|
| t0 | | | |
| | | |
| TS_core_selector | 22.222ns| 7.935ns| N/A|
0| 0| 4158| 0|
| TS_clkmgr_mmcm_inst_mmcm_clkou| 22.222ns| 13.218ns| N/A|
0| 0| 188| 0|
| t1 | | | |
| | | |
| TS_clkmgr_mmcm_inst_mmcm_clkou| 5.556ns| 5.588ns| N/A|
2| 0| 81931| 0|
| t2 | | | |
| | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock fmc_clk
------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process |
| Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal
Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
fmc_a<0> | 7.252(R)| SLOW | -4.231(R)| FAST |io_clk
| -2.777|
fmc_a<1> | 7.417(R)| SLOW | -4.285(R)| FAST |io_clk
| -2.777|
fmc_a<2> | 7.374(R)| SLOW | -4.273(R)| FAST |io_clk
| -2.777|
fmc_a<3> | 7.258(R)| SLOW | -4.226(R)| FAST |io_clk
| -2.777|
fmc_a<4> | 7.250(R)| SLOW | -4.247(R)| FAST |io_clk
| -2.777|
fmc_a<5> | 7.402(R)| SLOW | -4.323(R)| FAST |io_clk
| -2.777|
fmc_a<6> | 7.309(R)| SLOW | -4.292(R)| FAST |io_clk
| -2.777|
fmc_a<7> | 7.419(R)| SLOW | -4.317(R)| FAST |io_clk
| -2.777|
fmc_a<8> | 7.290(R)| SLOW | -4.272(R)| FAST |io_clk
| -2.777|
fmc_a<9> | 7.298(R)| SLOW | -4.289(R)| FAST |io_clk
| -2.777|
fmc_a<10> | 7.420(R)| SLOW | -4.318(R)| FAST |io_clk
| -2.777|
fmc_a<11> | 7.464(R)| SLOW | -4.366(R)| FAST |io_clk
| -2.777|
fmc_a<12> | 8.781(R)| SLOW | -4.817(R)| FAST |io_clk
| -2.777|
fmc_a<13> | 8.700(R)| SLOW | -4.806(R)| FAST |io_clk
| -2.777|
fmc_a<14> | 8.854(R)| SLOW | -4.891(R)| FAST |io_clk
| -2.777|
fmc_a<15> | 9.121(R)| SLOW | -5.093(R)| FAST |io_clk
| -2.777|
fmc_a<16> | 9.276(R)| SLOW | -5.165(R)| FAST |io_clk
| -2.777|
fmc_a<17> | 9.212(R)| SLOW | -5.104(R)| FAST |io_clk
| -2.777|
fmc_a<18> | 8.806(R)| SLOW | -4.897(R)| FAST |io_clk
| -2.777|
fmc_a<19> | 9.454(R)| SLOW | -5.236(R)| FAST |io_clk
| -2.777|
fmc_a<20> | 7.501(R)| SLOW | -4.404(R)| FAST |io_clk
| -2.777|
fmc_a<21> | 7.467(R)| SLOW | -4.368(R)| FAST |io_clk
| -2.777|
fmc_a<22> | 7.538(R)| SLOW | -4.421(R)| FAST |io_clk
| -2.777|
fmc_a<23> | 7.768(R)| SLOW | -4.485(R)| FAST |io_clk
| -2.777|
fmc_d<0> | 6.017(R)| SLOW | -3.731(R)| FAST |io_clk
| -2.777|
fmc_d<1> | 6.010(R)| SLOW | -3.723(R)| FAST |io_clk
| -2.777|
fmc_d<2> | 6.004(R)| SLOW | -3.717(R)| FAST |io_clk
| -2.777|
fmc_d<3> | 6.003(R)| SLOW | -3.717(R)| FAST |io_clk
| -2.777|
fmc_d<4> | 5.849(R)| SLOW | -3.669(R)| FAST |io_clk
| -2.777|
fmc_d<5> | 5.851(R)| SLOW | -3.669(R)| FAST |io_clk
| -2.777|
fmc_d<6> | 5.844(R)| SLOW | -3.662(R)| FAST |io_clk
| -2.777|
fmc_d<7> | 5.841(R)| SLOW | -3.658(R)| FAST |io_clk
| -2.777|
fmc_d<8> | 6.012(R)| SLOW | -3.734(R)| FAST |io_clk
| -2.777|
fmc_d<9> | 6.013(R)| SLOW | -3.738(R)| FAST |io_clk
| -2.777|
fmc_d<10> | 6.000(R)| SLOW | -3.723(R)| FAST |io_clk
| -2.777|
fmc_d<11> | 5.923(R)| SLOW | -3.650(R)| FAST |io_clk
| -2.777|
fmc_d<12> | 5.996(R)| SLOW | -3.719(R)| FAST |io_clk
| -2.777|
fmc_d<13> | 6.032(R)| SLOW | -3.744(R)| FAST |io_clk
| -2.777|
fmc_d<14> | 6.042(R)| SLOW | -3.754(R)| FAST |io_clk
| -2.777|
fmc_d<15> | 6.041(R)| SLOW | -3.752(R)| FAST |io_clk
| -2.777|
fmc_d<16> | 6.033(R)| SLOW | -3.745(R)| FAST |io_clk
| -2.777|
fmc_d<17> | 6.024(R)| SLOW | -3.735(R)| FAST |io_clk
| -2.777|
fmc_d<18> | 6.028(R)| SLOW | -3.739(R)| FAST |io_clk
| -2.777|
fmc_d<19> | 6.032(R)| SLOW | -3.742(R)| FAST |io_clk
| -2.777|
fmc_d<20> | 6.040(R)| SLOW | -3.749(R)| FAST |io_clk
| -2.777|
fmc_d<21> | 6.024(R)| SLOW | -3.735(R)| FAST |io_clk
| -2.777|
fmc_d<22> | 6.027(R)| SLOW | -3.738(R)| FAST |io_clk
| -2.777|
fmc_d<23> | 6.017(R)| SLOW | -3.726(R)| FAST |io_clk
| -2.777|
fmc_d<24> | 5.861(R)| SLOW | -3.677(R)| FAST |io_clk
| -2.777|
fmc_d<25> | 5.998(R)| SLOW | -3.708(R)| FAST |io_clk
| -2.777|
fmc_d<26> | 5.841(R)| SLOW | -3.658(R)| FAST |io_clk
| -2.777|
fmc_d<27> | 5.829(R)| SLOW | -3.649(R)| FAST |io_clk
| -2.777|
fmc_d<28> | 5.997(R)| SLOW | -3.720(R)| FAST |io_clk
| -2.777|
fmc_d<29> | 5.993(R)| SLOW | -3.717(R)| FAST |io_clk
| -2.777|
fmc_d<30> | 5.974(R)| SLOW | -3.701(R)| FAST |io_clk
| -2.777|
fmc_d<31> | 5.964(R)| SLOW | -3.691(R)| FAST |io_clk
| -2.777|
fmc_ne1 | 7.272(R)| SLOW | -4.256(R)| FAST |io_clk
| -2.777|
fmc_nl | 7.459(R)| SLOW | -4.329(R)| FAST |io_clk
| -2.777|
fmc_nwe | 7.229(R)| SLOW | -4.239(R)| FAST |io_clk
| -2.777|
------------+------------+------------+------------+------------+------------------+--------+
Clock fmc_clk to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process |
| Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner
|Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
fmc_d<0> | 0.066(F)| SLOW | -1.930(F)| FAST
|io_clk | -2.777|
fmc_d<1> | 0.059(F)| SLOW | -1.938(F)| FAST
|io_clk | -2.777|
fmc_d<2> | 0.058(F)| SLOW | -1.940(F)| FAST
|io_clk | -2.777|
fmc_d<3> | 0.055(F)| SLOW | -1.942(F)| FAST
|io_clk | -2.777|
fmc_d<4> | 0.271(F)| SLOW | -1.844(F)| FAST
|io_clk | -2.777|
fmc_d<5> | 0.267(F)| SLOW | -1.846(F)| FAST
|io_clk | -2.777|
fmc_d<6> | 0.249(F)| SLOW | -1.861(F)| FAST
|io_clk | -2.777|
fmc_d<7> | 0.245(F)| SLOW | -1.864(F)| FAST
|io_clk | -2.777|
fmc_d<8> | 0.074(F)| SLOW | -1.928(F)| FAST
|io_clk | -2.777|
fmc_d<9> | 0.094(F)| SLOW | -1.913(F)| FAST
|io_clk | -2.777|
fmc_d<10> | 0.062(F)| SLOW | -1.939(F)| FAST
|io_clk | -2.777|
fmc_d<11> | 0.017(F)| SLOW | -1.992(F)| FAST
|io_clk | -2.777|
fmc_d<12> | 0.062(F)| SLOW | -1.941(F)| FAST
|io_clk | -2.777|
fmc_d<13> | 0.074(F)| SLOW | -1.921(F)| FAST
|io_clk | -2.777|
fmc_d<14> | 0.085(F)| SLOW | -1.911(F)| FAST
|io_clk | -2.777|
fmc_d<15> | 0.082(F)| SLOW | -1.913(F)| FAST
|io_clk | -2.777|
fmc_d<16> | 0.074(F)| SLOW | -1.921(F)| FAST
|io_clk | -2.777|
fmc_d<17> | 0.061(F)| SLOW | -1.933(F)| FAST
|io_clk | -2.777|
fmc_d<18> | 0.064(F)| SLOW | -1.929(F)| FAST
|io_clk | -2.777|
fmc_d<19> | 0.060(F)| SLOW | -1.930(F)| FAST
|io_clk | -2.777|
fmc_d<20> | 0.067(F)| SLOW | -1.923(F)| FAST
|io_clk | -2.777|
fmc_d<21> | 0.050(F)| SLOW | -1.941(F)| FAST
|io_clk | -2.777|
fmc_d<22> | 0.053(F)| SLOW | -1.938(F)| FAST
|io_clk | -2.777|
fmc_d<23> | 0.039(F)| SLOW | -1.951(F)| FAST
|io_clk | -2.777|
fmc_d<24> | 0.267(F)| SLOW | -1.842(F)| FAST
|io_clk | -2.777|
fmc_d<25> | 0.020(F)| SLOW | -1.970(F)| FAST
|io_clk | -2.777|
fmc_d<26> | 0.242(F)| SLOW | -1.867(F)| FAST
|io_clk | -2.777|
fmc_d<27> | 0.256(F)| SLOW | -1.859(F)| FAST
|io_clk | -2.777|
fmc_d<28> | 0.063(F)| SLOW | -1.940(F)| FAST
|io_clk | -2.777|
fmc_d<29> | 0.059(F)| SLOW | -1.943(F)| FAST
|io_clk | -2.777|
fmc_d<30> | 0.066(F)| SLOW | -1.944(F)| FAST
|io_clk | -2.777|
fmc_d<31> | 0.056(F)| SLOW | -1.953(F)| FAST
|io_clk | -2.777|
------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock fmc_clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
fmc_clk | 11.098| | 6.609| |
---------------+---------+---------+---------+---------+
TIMEGRP "TNM_FMC_IN_DATA" OFFSET = IN 7.5 ns VALID 17.5 ns BEFORE COMP
"fmc_clk" "RISING";
Worst Case Data Window 2.393; Ideal Clock Offset To Actual Clock 6.095;
------------------+------------+------------+------------+------------+---------+---------+-------------+
| | Process | | Process | Setup
| Hold |Source Offset|
Source | Setup | Corner | Hold | Corner | Slack
| Slack | To Center |
------------------+------------+------------+------------+------------+---------+---------+-------------+
fmc_d<0> | 6.017(R)| SLOW | -3.731(R)| FAST |
1.483| 13.731| -6.124|
fmc_d<1> | 6.010(R)| SLOW | -3.723(R)| FAST |
1.490| 13.723| -6.117|
fmc_d<2> | 6.004(R)| SLOW | -3.717(R)| FAST |
1.496| 13.717| -6.111|
fmc_d<3> | 6.003(R)| SLOW | -3.717(R)| FAST |
1.497| 13.717| -6.110|
fmc_d<4> | 5.849(R)| SLOW | -3.669(R)| FAST |
1.651| 13.669| -6.009|
fmc_d<5> | 5.851(R)| SLOW | -3.669(R)| FAST |
1.649| 13.669| -6.010|
fmc_d<6> | 5.844(R)| SLOW | -3.662(R)| FAST |
1.656| 13.662| -6.003|
fmc_d<7> | 5.841(R)| SLOW | -3.658(R)| FAST |
1.659| 13.658| -5.999|
fmc_d<8> | 6.012(R)| SLOW | -3.734(R)| FAST |
1.488| 13.734| -6.123|
fmc_d<9> | 6.013(R)| SLOW | -3.738(R)| FAST |
1.487| 13.738| -6.126|
fmc_d<10> | 6.000(R)| SLOW | -3.723(R)| FAST |
1.500| 13.723| -6.112|
fmc_d<11> | 5.923(R)| SLOW | -3.650(R)| FAST |
1.577| 13.650| -6.037|
fmc_d<12> | 5.996(R)| SLOW | -3.719(R)| FAST |
1.504| 13.719| -6.108|
fmc_d<13> | 6.032(R)| SLOW | -3.744(R)| FAST |
1.468| 13.744| -6.138|
fmc_d<14> | 6.042(R)| SLOW | -3.754(R)| FAST |
1.458| 13.754| -6.148|
fmc_d<15> | 6.041(R)| SLOW | -3.752(R)| FAST |
1.459| 13.752| -6.147|
fmc_d<16> | 6.033(R)| SLOW | -3.745(R)| FAST |
1.467| 13.745| -6.139|
fmc_d<17> | 6.024(R)| SLOW | -3.735(R)| FAST |
1.476| 13.735| -6.130|
fmc_d<18> | 6.028(R)| SLOW | -3.739(R)| FAST |
1.472| 13.739| -6.134|
fmc_d<19> | 6.032(R)| SLOW | -3.742(R)| FAST |
1.468| 13.742| -6.137|
fmc_d<20> | 6.040(R)| SLOW | -3.749(R)| FAST |
1.460| 13.749| -6.145|
fmc_d<21> | 6.024(R)| SLOW | -3.735(R)| FAST |
1.476| 13.735| -6.130|
fmc_d<22> | 6.027(R)| SLOW | -3.738(R)| FAST |
1.473| 13.738| -6.132|
fmc_d<23> | 6.017(R)| SLOW | -3.726(R)| FAST |
1.483| 13.726| -6.122|
fmc_d<24> | 5.861(R)| SLOW | -3.677(R)| FAST |
1.639| 13.677| -6.019|
fmc_d<25> | 5.998(R)| SLOW | -3.708(R)| FAST |
1.502| 13.708| -6.103|
fmc_d<26> | 5.841(R)| SLOW | -3.658(R)| FAST |
1.659| 13.658| -5.999|
fmc_d<27> | 5.829(R)| SLOW | -3.649(R)| FAST |
1.671| 13.649| -5.989|
fmc_d<28> | 5.997(R)| SLOW | -3.720(R)| FAST |
1.503| 13.720| -6.109|
fmc_d<29> | 5.993(R)| SLOW | -3.717(R)| FAST |
1.507| 13.717| -6.105|
fmc_d<30> | 5.974(R)| SLOW | -3.701(R)| FAST |
1.526| 13.701| -6.088|
fmc_d<31> | 5.964(R)| SLOW | -3.691(R)| FAST |
1.536| 13.691| -6.078|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary| 6.042| - | -3.649| - |
1.458| 13.649| |
------------------+------------+------------+------------+------------+---------+---------+-------------+
TIMEGRP "TNM_FMC_IN_ADDR" OFFSET = IN 10 ns VALID 9 ns BEFORE COMP "fmc_clk"
"RISING";
Worst Case Data Window 5.228; Ideal Clock Offset To Actual Clock 1.340;
------------------+------------+------------+------------+------------+---------+---------+-------------+
| | Process | | Process | Setup
| Hold |Source Offset|
Source | Setup | Corner | Hold | Corner | Slack
| Slack | To Center |
------------------+------------+------------+------------+------------+---------+---------+-------------+
fmc_a<0> | 7.252(R)| SLOW | -4.231(R)| FAST |
2.748| 3.231| -0.241|
fmc_a<1> | 7.417(R)| SLOW | -4.285(R)| FAST |
2.583| 3.285| -0.351|
fmc_a<2> | 7.374(R)| SLOW | -4.273(R)| FAST |
2.626| 3.273| -0.324|
fmc_a<3> | 7.258(R)| SLOW | -4.226(R)| FAST |
2.742| 3.226| -0.242|
fmc_a<4> | 7.250(R)| SLOW | -4.247(R)| FAST |
2.750| 3.247| -0.248|
fmc_a<5> | 7.402(R)| SLOW | -4.323(R)| FAST |
2.598| 3.323| -0.363|
fmc_a<6> | 7.309(R)| SLOW | -4.292(R)| FAST |
2.691| 3.292| -0.301|
fmc_a<7> | 7.419(R)| SLOW | -4.317(R)| FAST |
2.581| 3.317| -0.368|
fmc_a<8> | 7.290(R)| SLOW | -4.272(R)| FAST |
2.710| 3.272| -0.281|
fmc_a<9> | 7.298(R)| SLOW | -4.289(R)| FAST |
2.702| 3.289| -0.294|
fmc_a<10> | 7.420(R)| SLOW | -4.318(R)| FAST |
2.580| 3.318| -0.369|
fmc_a<11> | 7.464(R)| SLOW | -4.366(R)| FAST |
2.536| 3.366| -0.415|
fmc_a<12> | 8.781(R)| SLOW | -4.817(R)| FAST |
1.219| 3.817| -1.299|
fmc_a<13> | 8.700(R)| SLOW | -4.806(R)| FAST |
1.300| 3.806| -1.253|
fmc_a<14> | 8.854(R)| SLOW | -4.891(R)| FAST |
1.146| 3.891| -1.373|
fmc_a<15> | 9.121(R)| SLOW | -5.093(R)| FAST |
0.879| 4.093| -1.607|
fmc_a<16> | 9.276(R)| SLOW | -5.165(R)| FAST |
0.724| 4.165| -1.721|
fmc_a<17> | 9.212(R)| SLOW | -5.104(R)| FAST |
0.788| 4.104| -1.658|
fmc_a<18> | 8.806(R)| SLOW | -4.897(R)| FAST |
1.194| 3.897| -1.352|
fmc_a<19> | 9.454(R)| SLOW | -5.236(R)| FAST |
0.546| 4.236| -1.845|
fmc_a<20> | 7.501(R)| SLOW | -4.404(R)| FAST |
2.499| 3.404| -0.452|
fmc_a<21> | 7.467(R)| SLOW | -4.368(R)| FAST |
2.533| 3.368| -0.418|
fmc_a<22> | 7.538(R)| SLOW | -4.421(R)| FAST |
2.462| 3.421| -0.479|
fmc_a<23> | 7.768(R)| SLOW | -4.485(R)| FAST |
2.232| 3.485| -0.626|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary| 9.454| - | -4.226| - |
0.546| 3.226| |
------------------+------------+------------+------------+------------+---------+---------+-------------+
TIMEGRP "TNM_FMC_IN_CONTROL" OFFSET = IN 9.5 ns VALID 13.5 ns BEFORE COMP
"fmc_clk" "RISING";
Worst Case Data Window 3.220; Ideal Clock Offset To Actual Clock 3.099;
------------------+------------+------------+------------+------------+---------+---------+-------------+
| | Process | | Process | Setup
| Hold |Source Offset|
Source | Setup | Corner | Hold | Corner | Slack
| Slack | To Center |
------------------+------------+------------+------------+------------+---------+---------+-------------+
fmc_ne1 | 7.272(R)| SLOW | -4.256(R)| FAST |
2.228| 8.256| -3.014|
fmc_nl | 7.459(R)| SLOW | -4.329(R)| FAST |
2.041| 8.329| -3.144|
fmc_nwe | 7.229(R)| SLOW | -4.239(R)| FAST |
2.271| 8.239| -2.984|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary| 7.459| - | -4.239| - |
2.041| 8.239| |
------------------+------------+------------+------------+------------+---------+---------+-------------+
TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 6 ns BEFORE COMP "fmc_clk" "FALLING";
Bus Skew: 0.254 ns;
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
|Max (slowest)| Process |Min
(fastest)| Process | |
PAD | Delay (ns) | Corner |
Delay (ns) | Corner |Edge Skew (ns)|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
fmc_d<0> | 0.066| SLOW |
-1.930| FAST | 0.049|
fmc_d<1> | 0.059| SLOW |
-1.938| FAST | 0.042|
fmc_d<2> | 0.058| SLOW |
-1.940| FAST | 0.041|
fmc_d<3> | 0.055| SLOW |
-1.942| FAST | 0.038|
fmc_d<4> | 0.271| SLOW |
-1.844| FAST | 0.254|
fmc_d<5> | 0.267| SLOW |
-1.846| FAST | 0.250|
fmc_d<6> | 0.249| SLOW |
-1.861| FAST | 0.232|
fmc_d<7> | 0.245| SLOW |
-1.864| FAST | 0.228|
fmc_d<8> | 0.074| SLOW |
-1.928| FAST | 0.057|
fmc_d<9> | 0.094| SLOW |
-1.913| FAST | 0.077|
fmc_d<10> | 0.062| SLOW |
-1.939| FAST | 0.045|
fmc_d<11> | 0.017| SLOW |
-1.992| FAST | 0.000|
fmc_d<12> | 0.062| SLOW |
-1.941| FAST | 0.045|
fmc_d<13> | 0.074| SLOW |
-1.921| FAST | 0.057|
fmc_d<14> | 0.085| SLOW |
-1.911| FAST | 0.068|
fmc_d<15> | 0.082| SLOW |
-1.913| FAST | 0.065|
fmc_d<16> | 0.074| SLOW |
-1.921| FAST | 0.057|
fmc_d<17> | 0.061| SLOW |
-1.933| FAST | 0.044|
fmc_d<18> | 0.064| SLOW |
-1.929| FAST | 0.047|
fmc_d<19> | 0.060| SLOW |
-1.930| FAST | 0.043|
fmc_d<20> | 0.067| SLOW |
-1.923| FAST | 0.050|
fmc_d<21> | 0.050| SLOW |
-1.941| FAST | 0.033|
fmc_d<22> | 0.053| SLOW |
-1.938| FAST | 0.036|
fmc_d<23> | 0.039| SLOW |
-1.951| FAST | 0.022|
fmc_d<24> | 0.267| SLOW |
-1.842| FAST | 0.250|
fmc_d<25> | 0.020| SLOW |
-1.970| FAST | 0.003|
fmc_d<26> | 0.242| SLOW |
-1.867| FAST | 0.225|
fmc_d<27> | 0.256| SLOW |
-1.859| FAST | 0.239|
fmc_d<28> | 0.063| SLOW |
-1.940| FAST | 0.046|
fmc_d<29> | 0.059| SLOW |
-1.943| FAST | 0.042|
fmc_d<30> | 0.066| SLOW |
-1.944| FAST | 0.049|
fmc_d<31> | 0.056| SLOW |
-1.953| FAST | 0.039|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
Timing summary:
---------------
Timing errors: 2 Score: 53 (Setup/Max: 53, Hold: 0)
Constraints cover 17372068 paths, 0 nets, and 261411 connections
Design statistics:
Minimum period: 13.218ns (Maximum frequency: 75.654MHz)
Maximum path delay from/to any node: 7.935ns
Minimum input required time before clock: 9.454ns
Maximum output delay after clock: 21.951ns
Analysis completed Tue Feb 25 20:14:21 2020
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 2006 MB
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