This is part of an effort to curb the macro abuse
in atw. Please test.
Index: atw.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/atw.c,v
retrieving revision 1.69
diff -u -p -r1.69 atw.c
--- atw.c 16 Aug 2009 18:03:48 -0000 1.69
+++ atw.c 16 Aug 2009 22:52:06 -0000
@@ -672,7 +672,7 @@ atw_attach(struct atw_softc *sc)
* MARVEL. My bug, or theirs?
*/
- reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);
+ reg = sc->sc_rftype << ATW_SYNCTL_RFTYPE_SHIFT;
switch (sc->sc_rftype) {
case ATW_RFTYPE_INTERSIL:
@@ -688,7 +688,7 @@ atw_attach(struct atw_softc *sc)
sc->sc_synctl_rd = reg | ATW_SYNCTL_RD;
sc->sc_synctl_wr = reg | ATW_SYNCTL_WR;
- reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);
+ reg = sc->sc_bbptype << ATW_BBPCTL_TYPE_SHIFT;
switch (sc->sc_bbptype) {
case ATW_BBPTYPE_INTERSIL:
@@ -1024,7 +1024,7 @@ atw_wcsr_init(struct atw_softc *sc)
wcsr = ATW_READ(sc, ATW_WCSR);
wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE);
- wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK);
+ wcsr |= (7 << ATW_WCSR_BLN_SHIFT);
ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */
DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n",
@@ -1051,24 +1051,24 @@ atw_tofs2_init(struct atw_softc *sc)
uint32_t tofs2;
/* XXX this magic can probably be figured out from the RFMD docs */
#ifndef ATW_REFSLAVE
- tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
- LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
- LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
- LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
- LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
- LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
- LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
- LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
+ tofs2 = (4 << ATW_TOFS2_PWR1UP_SHIFT) | /* 8 ms = 4 * 2 ms */
+ (13 << ATW_TOFS2_PWR0PAPE_SHIFT) | /* 13 us */
+ (8 << ATW_TOFS2_PWR1PAPE_SHIFT) | /* 8 us */
+ (5 << ATW_TOFS2_PWR0TRSW_SHIFT) | /* 5 us */
+ (12 << ATW_TOFS2_PWR1TRSW_SHIFT) | /* 12 us */
+ (13 << ATW_TOFS2_PWR0PE2_SHIFT) | /* 13 us */
+ (4 << ATW_TOFS2_PWR1PE2_SHIFT) | /* 4 us */
+ (5 << ATW_TOFS2_PWR0TXPE_SHIFT); /* 5 us */
#else
/* XXX new magic from reference driver source */
- tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
- LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
- LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
- LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
- LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
- LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
- LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
- LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
+ tofs2 = (8 << ATW_TOFS2_PWR1UP_SHIFT) | /* 8 ms = 4 * 2 ms */
+ (8 << ATW_TOFS2_PWR0PAPE_SHIFT) | /* 13 us */
+ (1 << ATW_TOFS2_PWR1PAPE_SHIFT) | /* 8 us */
+ (5 << ATW_TOFS2_PWR0TRSW_SHIFT) | /* 5 us */
+ (12 << ATW_TOFS2_PWR1TRSW_SHIFT) | /* 12 us */
+ (13 << ATW_TOFS2_PWR0PE2_SHIFT) | /* 13 us */
+ (1 << ATW_TOFS2_PWR1PE2_SHIFT) | /* 4 us */
+ (8 << ATW_TOFS2_PWR0TXPE_SHIFT); /* 5 us */
#endif
ATW_WRITE(sc, ATW_TOFS2, tofs2);
}
@@ -1082,8 +1082,8 @@ atw_nar_init(struct atw_softc *sc)
void
atw_txlmt_init(struct atw_softc *sc)
{
- ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) |
- LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK));
+ ATW_WRITE(sc, ATW_TXLMT, (512 << ATW_TXLMT_MTMLT_SHIFT) |
+ (1 << ATW_TXLMT_SRTYLIM_SHIFT));
}
void
@@ -1094,7 +1094,7 @@ atw_test1_init(struct atw_softc *sc)
test1 = ATW_READ(sc, ATW_TEST1);
test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL);
/* XXX magic 0x1 */
- test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL;
+ test1 |= (0x1 << ATW_TEST1_DBGREAD_SHIFT) | ATW_TEST1_CONTROL;
ATW_WRITE(sc, ATW_TEST1, test1);
}
@@ -1117,7 +1117,7 @@ atw_cfp_init(struct atw_softc *sc)
cfpp = ATW_READ(sc, ATW_CFPP);
cfpp &= ~ATW_CFPP_CFPMD;
- cfpp |= LSHIFT(16, ATW_CFPP_CFPMD);
+ cfpp |= (16 << ATW_CFPP_CFPMD_SHIFT);
ATW_WRITE(sc, ATW_CFPP, cfpp);
}
@@ -1133,7 +1133,7 @@ atw_tofs0_init(struct atw_softc *sc)
* these values. These values are also the power-on default.
*/
ATW_WRITE(sc, ATW_TOFS0,
- LSHIFT(22, ATW_TOFS0_USCNT_MASK) |
+ (22 << ATW_TOFS0_USCNT_SHIFT) |
ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */);
}
@@ -1145,11 +1145,11 @@ atw_ifs_init(struct atw_softc *sc)
/* XXX EIFS=0x64, SIFS=110 are used by the reference driver.
* Go figure.
*/
- ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |
- LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */,
- ATW_IFST_SIFS_MASK) |
- LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |
- LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK);
+ ifst = (IEEE80211_DUR_DS_SLOT << ATW_IFST_SLOT_SHIFT) |
+ /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */
+ ((22 * 5) << ATW_IFST_SIFS_SHIFT) |
+ (IEEE80211_DUR_DS_DIFS << ATW_IFST_DIFS_SHIFT) |
+ (0x64 << ATW_IFST_EIFS_SHIFT);
ATW_WRITE(sc, ATW_IFST, ifst);
}
@@ -1163,8 +1163,8 @@ atw_response_times_init(struct atw_softc
* it waits at most SIFS + MART microseconds for the response.
* Surely this is not the ACK timeout?
*/
- ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) |
- LSHIFT(0xff, ATW_RSPT_MIRT_MASK));
+ ATW_WRITE(sc, ATW_RSPT, (0xffff << ATW_RSPT_MART_SHIFT) |
+ (0xff << ATW_RSPT_MIRT_SHIFT));
}
/* Set up the MMI read/write addresses for the baseband. The Tx/Rx
@@ -1270,8 +1270,8 @@ atw_init(struct ifnet *ifp)
*
* XXX Set transmit power for ATIM, RTS, Beacon.
*/
- ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) |
- LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK));
+ ATW_WRITE(sc, ATW_PLCPHD, (10 << ATW_PLCPHD_SIGNAL_SHIFT) |
+ (0xb0 << ATW_PLCPHD_SERVICE_SHIFT));
atw_tofs2_init(sc);
@@ -1293,7 +1293,7 @@ atw_init(struct ifnet *ifp)
* XXX A frame may only dribble in for 65536us.
*/
ATW_WRITE(sc, ATW_RMD,
- LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK));
+ (1 << ATW_RMD_PCNT_SHIFT) | (0xffff << ATW_RMD_RMRD_SHIFT));
atw_response_times_init(sc);
@@ -1629,7 +1629,7 @@ atw_si4126_tune(struct atw_softc *sc, u_
* REFDIF This is different from the reference driver, which
* always sets SI4126_GAIN to 0.
*/
- gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK);
+ gain = ((((mhz - 374) > 2047) ? 1 : 0) << SI4126_GAIN_KP2_SHIFT);
atw_si4126_write(sc, SI4126_GAIN, gain);
@@ -1668,7 +1668,7 @@ atw_si4126_tune(struct atw_softc *sc, u_
gpio = ATW_READ(sc, ATW_GPIO);
gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK);
- gpio |= LSHIFT(1, ATW_GPIO_EN_MASK);
+ gpio |= (1 << ATW_GPIO_EN_SHIFT);
if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) {
/* Set a Prism RF front-end to a special mode for channel 14?
@@ -1676,7 +1676,7 @@ atw_si4126_tune(struct atw_softc *sc, u_
* Apparently the SMC2635W needs this, although I don't think
* it has a Prism RF.
*/
- gpio |= LSHIFT(1, ATW_GPIO_O_MASK);
+ gpio |= (1 << ATW_GPIO_O_SHIFT);
}
ATW_WRITE(sc, ATW_GPIO, gpio);
@@ -1701,7 +1701,7 @@ atw_rf3000_init(struct atw_softc *sc)
/* CCA is acquisition sensitive */
rc = atw_rf3000_write(sc, RF3000_CCACTL,
- LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK));
+ (RF3000_CCACTL_MODE_BOTH << RF3000_CCACTL_MODE_SHIFT));
if (rc != 0)
goto out;
@@ -1714,14 +1714,14 @@ atw_rf3000_init(struct atw_softc *sc)
/* sensible setting from a binary-only driver */
rc = atw_rf3000_write(sc, RF3000_GAINCTL,
- LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK));
+ (0x1d << RF3000_GAINCTL_TXVGC_SHIFT));
if (rc != 0)
goto out;
/* magic from a binary-only driver */
rc = atw_rf3000_write(sc, RF3000_LOGAINCAL,
- LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK));
+ (0x38 << RF3000_LOGAINCAL_CAL_SHIFT));
if (rc != 0)
goto out;
@@ -1806,7 +1806,7 @@ atw_rf3000_tune(struct atw_softc *sc, u_
atw_bbp_io_enable(sc, 1);
if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL,
- LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0)
+ (txpower << RF3000_GAINCTL_TXVGC_SHIFT))) != 0)
goto out;
if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0)
@@ -1832,8 +1832,8 @@ out:
/* set beacon, rts, atim transmit power */
reg = ATW_READ(sc, ATW_PLCPHD);
reg &= ~ATW_PLCPHD_SERVICE_MASK;
- reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK),
- ATW_PLCPHD_SERVICE_MASK);
+ reg |= ((txpower << RF3000_GAINCTL_TXVGC_SHIFT) <<
+ ATW_PLCPHD_SERVICE_SHIFT);
ATW_WRITE(sc, ATW_PLCPHD, reg);
DELAY(2 * 1000);
@@ -1852,8 +1852,8 @@ atw_rf3000_write(struct atw_softc *sc, u
int i;
reg = sc->sc_bbpctl_wr |
- LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) |
- LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
+ ((val & 0xff) << ATW_BBPCTL_DATA_SHIFT) |
+ ((addr & 0x7f) << ATW_BBPCTL_ADDR_SHIFT);
for (i = 10; --i >= 0; ) {
ATW_WRITE(sc, ATW_BBPCTL, reg);
@@ -1901,7 +1901,7 @@ atw_rf3000_read(struct atw_softc *sc, u_
return ETIMEDOUT;
}
- reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
+ reg = sc->sc_bbpctl_rd | ((addr & 0x7f) << ATW_BBPCTL_ADDR_SHIFT);
ATW_WRITE(sc, ATW_BBPCTL, reg);
@@ -1949,8 +1949,8 @@ atw_si4126_write(struct atw_softc *sc, u
KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0);
KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
- bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
- LSHIFT(addr, SI4126_TWI_ADDR_MASK);
+ bits = (val << SI4126_TWI_DATA_SHIFT) |
+ (addr << SI4126_TWI_ADDR_SHIFT);
}
reg = ATW_SYNRF_SELSYN;
@@ -2000,7 +2000,7 @@ atw_si4126_read(struct atw_softc *sc, u_
return ETIMEDOUT;
}
- reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK);
+ reg = sc->sc_synctl_rd | (addr << ATW_SYNCTL_DATA_SHIFT);
ATW_WRITE(sc, ATW_SYNCTL, reg);
@@ -2113,16 +2113,16 @@ atw_write_bssid(struct atw_softc *sc)
bssid = ic->ic_bss->ni_bssid;
ATW_WRITE(sc, ATW_BSSID0,
- LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) |
- LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) |
- LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) |
- LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK));
+ (bssid[0] << ATW_BSSID0_BSSIDB0_SHIFT) |
+ (bssid[1] << ATW_BSSID0_BSSIDB1_SHIFT) |
+ (bssid[2] << ATW_BSSID0_BSSIDB2_SHIFT) |
+ (bssid[3] << ATW_BSSID0_BSSIDB3_SHIFT));
ATW_WRITE(sc, ATW_ABDA1,
(ATW_READ(sc, ATW_ABDA1) &
~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) |
- LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) |
- LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK));
+ (bssid[4] << ATW_ABDA1_BSSIDB4_SHIFT) |
+ (bssid[5] << ATW_ABDA1_BSSIDB5_SHIFT));
DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname,
ether_sprintf(sc->sc_bssid)));
@@ -2150,11 +2150,11 @@ atw_write_sram(struct atw_softc *sc, u_i
for (i = 0; i < buflen; i += 2) {
ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR |
- LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK));
+ (((ofs + i) / 2) << ATW_WEPCTL_TBLADD_SHIFT));
DELAY(atw_writewep_delay);
ATW_WRITE(sc, ATW_WESK,
- LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK));
+ (((ptr[i + 1] << 8) | ptr[i]) << ATW_WESK_DATA_SHIFT));
DELAY(atw_writewep_delay);
}
ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */
@@ -2212,7 +2212,7 @@ atw_write_wep(struct atw_softc *sc)
reg = ATW_READ(sc, ATW_MACTEST);
reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID;
reg &= ~ATW_MACTEST_KEYID_MASK;
- reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK);
+ reg |= (ic->ic_wep_txkey << ATW_MACTEST_KEYID_SHIFT);
ATW_WRITE(sc, ATW_MACTEST, reg);
sc->sc_wepctl = ATW_WEPCTL_WEPENABLE;
@@ -2371,14 +2371,14 @@ atw_start_beacon(struct atw_softc *sc, i
/* set listen interval
* XXX do software units agree w/ hardware?
*/
- bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
- LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK);
+ bpli = (ic->ic_bss->ni_intval << ATW_BPLI_BP_SHIFT) |
+ ((ic->ic_lintval / ic->ic_bss->ni_intval) << ATW_BPLI_LI_SHIFT);
chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan);
- bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK);
- cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK);
- cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK);
+ bcnt |= (len << ATW_BCNT_BCNT_SHIFT);
+ cap0 |= (chan << ATW_CAP0_CHN_SHIFT);
+ cap1 |= (capinfo << ATW_CAP1_CAPI_SHIFT);
ATW_WRITE(sc, ATW_BCNT, bcnt);
ATW_WRITE(sc, ATW_BPLI, bpli);
@@ -2475,10 +2475,10 @@ atw_predict_beacon(struct atw_softc *sc)
tbtt = past_even + ival * 10;
ATW_WRITE(sc, ATW_TOFS1,
- LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) |
- LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) |
- LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU,
- ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK));
+ (1 << ATW_TOFS1_TSFTOFSR_SHIFT) |
+ (TBTTOFS << ATW_TOFS1_TBTTOFS_SHIFT) |
+ (MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU,
+ ATW_TBTTPRE_MASK) << ATW_TOFS1_TBTTPRE_SHIFT));
#undef TBTTOFS
}
@@ -2545,9 +2545,9 @@ atw_newstate(struct ieee80211com *ic, en
* XXX do software units agree w/ hardware?
*/
ATW_WRITE(sc, ATW_BPLI,
- LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
- LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval,
- ATW_BPLI_LI_MASK));
+ (ic->ic_bss->ni_intval << ATW_BPLI_BP_SHIFT) |
+ ((ic->ic_lintval / ic->ic_bss->ni_intval) <<
+ ATW_BPLI_LI_SHIFT));
DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n",
sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI)));
@@ -3864,11 +3864,11 @@ atw_start(struct ifnet *ifp)
/* XXX arbitrary retry limit; 8 because I have seen it in
* use already and maybe 0 means "no tries" !
*/
- ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK));
+ ctl = htole32(8 << ATW_TXCTL_TL_SHIFT);
DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n",
sc->sc_dev.dv_xname, rate * 5));
- ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK));
+ ctl |= htole32((MAX(10, rate * 5) << ATW_TXCTL_TXDR_SHIFT));
/*
* Initialize the transmit descriptors.
@@ -3888,8 +3888,8 @@ atw_start(struct ifnet *ifp)
txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr);
txd->at_flags =
- htole32(LSHIFT(dmamap->dm_segs[seg].ds_len,
- ATW_TXFLAG_TBS1_MASK)) |
+ htole32(dmamap->dm_segs[seg].ds_len <<
+ ATW_TXFLAG_TBS1_SHIFT) |
((nexttx == (ATW_NTXDESC - 1))
? htole32(ATW_TXFLAG_TER) : 0);
lasttx = nexttx;
Index: atwreg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/atwreg.h,v
retrieving revision 1.7
diff -u -p -r1.7 atwreg.h
--- atwreg.h 16 Aug 2009 18:03:48 -0000 1.7
+++ atwreg.h 16 Aug 2009 22:52:07 -0000
@@ -75,8 +75,6 @@
: MASK_TO_SHIFT16((m)))
#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))
-#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask))
-#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
#define PRESHIFT(m) MASK_AND_RSHIFT((m), (m))
#endif /* _BIT_TWIDDLE */
@@ -181,21 +179,23 @@
* receive suspended state
*/
#define ATW_PAR_CAL_MASK 0xc000 /* cache alignment */
+#define ATW_PAR_CAL_SHIFT 14
#define ATW_PAR_CAL_PBL 0x0
/* min(8 DW, PBL) */
-#define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK)
+#define ATW_PAR_CAL_8DW (0x1 << ATW_PAR_CAL_SHIFT)
/* min(16 DW, PBL) */
-#define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK)
+#define ATW_PAR_CAL_16DW (0x2 << ATW_PAR_CAL_SHIFT)
/* min(32 DW, PBL) */
-#define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK)
+#define ATW_PAR_CAL_32DW (0x3 << ATW_PAR_CAL_SHIFT)
#define ATW_PAR_PBL_MASK 0x3f00 /* programmable burst length */
+#define ATW_PAR_PBL_SHIFT 8
#define ATW_PAR_PBL_UNLIMITED 0x0
-#define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK)
-#define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK)
-#define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK)
-#define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK)
-#define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK)
-#define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK)
+#define ATW_PAR_PBL_1DW (0x1 << ATW_PAR_PBL_SHIFT)
+#define ATW_PAR_PBL_2DW (0x2 << ATW_PAR_PBL_SHIFT)
+#define ATW_PAR_PBL_4DW (0x4 << ATW_PAR_PBL_SHIFT)
+#define ATW_PAR_PBL_8DW (0x8 << ATW_PAR_PBL_SHIFT)
+#define ATW_PAR_PBL_16DW (0x16 << ATW_PAR_PBL_SHIFT)
+#define ATW_PAR_PBL_32DW (0x32 << ATW_PAR_PBL_SHIFT)
#define ATW_PAR_BLE (1<<7) /* big/little endian selection
*/
#define ATW_PAR_DSL_MASK 0x7c /* descriptor skip length */
#define ATW_PAR_BAR (1<<1) /* bus arbitration */
@@ -306,16 +306,17 @@
* TX threshold
*/
#define ATW_NAR_TR_MASK 0xc000 /* TX threshold */
-#define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK)
-#define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK)
-#define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK)
-#define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK)
-#define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK)
-#define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK)
+#define ATW_NAR_TR_SHIFT 14
+#define ATW_NAR_TR_L64 (0x0 << ATW_NAR_TR_SHIFT)
+#define ATW_NAR_TR_L160 (0x2 << ATW_NAR_TR_SHIFT)
+#define ATW_NAR_TR_L192 (0x3 << ATW_NAR_TR_SHIFT)
+#define ATW_NAR_TR_H96 (0x0 << ATW_NAR_TR_SHIFT)
+#define ATW_NAR_TR_H288 (0x2 << ATW_NAR_TR_SHIFT)
+#define ATW_NAR_TR_H544 (0x3 << ATW_NAR_TR_SHIFT)
#define ATW_NAR_ST (1<<13) /* start/stop transmit */
#define ATW_NAR_OM_MASK 0xc00 /* operating mode */
#define ATW_NAR_OM_NORMAL 0x0
-#define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK)
+#define ATW_NAR_OM_LOOPBACK (0x1 << ATW_NAR_OM_SHIFT)
#define ATW_NAR_MM (1<<7) /* RX any multicast */
#define ATW_NAR_PR (1<<6) /* promiscuous mode */
#define ATW_NAR_EA (1<<5) /* match ad hoc packets (?) */
@@ -373,21 +374,24 @@
#define ATW_TEST1_DBGREAD_MASK 0x70000000 /* "control of read
data,
* debug only"
*/
+#define ATW_TEST1_DBGREAD_SHIFT 28
#define ATW_TEST1_TXWP_MASK 0xe000000 /* select ATW_WTDP
content? */
-#define ATW_TEST1_TXWP_TDBD LSHIFT(0x0, ATW_TEST1_TXWP_MASK)
-#define ATW_TEST1_TXWP_TDBH LSHIFT(0x1, ATW_TEST1_TXWP_MASK)
-#define ATW_TEST1_TXWP_TDBB LSHIFT(0x2, ATW_TEST1_TXWP_MASK)
-#define ATW_TEST1_TXWP_TDBP LSHIFT(0x3, ATW_TEST1_TXWP_MASK)
+#define ATW_TEST1_TXWP_TDBD (0x0 << ATW_TEST1_TXWP_SHIFT)
+#define ATW_TEST1_TXWP_TDBH (0x1 << ATW_TEST1_TXWP_SHIFT)
+#define ATW_TEST1_TXWP_TDBB (0x2 << ATW_TEST1_TXWP_SHIFT)
+#define ATW_TEST1_TXWP_TDBP (0x3 << ATW_TEST1_TXWP_SHIFT)
#define ATW_TEST1_RSVD0_MASK 0x1ffffc0 /* reserved */
#define ATW_TEST1_TESTMODE_MASK 0x30
+#define ATW_TEST1_TESTMODE_SHIFT 4
+
/* normal operation */
-#define ATW_TEST1_TESTMODE_NORMAL LSHIFT(0x0,
ATW_TEST1_TESTMODE_MASK)
+#define ATW_TEST1_TESTMODE_NORMAL (0x0 <<
ATW_TEST1_TESTMODE_SHIFT)
/* MAC-only mode */
-#define ATW_TEST1_TESTMODE_MACONLY LSHIFT(0x1,
ATW_TEST1_TESTMODE_MASK)
+#define ATW_TEST1_TESTMODE_MACONLY (0x1 <<
ATW_TEST1_TESTMODE_SHIFT)
/* normal operation */
-#define ATW_TEST1_TESTMODE_NORMAL2 LSHIFT(0x2,
ATW_TEST1_TESTMODE_MASK)
+#define ATW_TEST1_TESTMODE_NORMAL2 (0x2 <<
ATW_TEST1_TESTMODE_SHIFT)
/* monitor mode */
-#define ATW_TEST1_TESTMODE_MONITOR LSHIFT(0x3,
ATW_TEST1_TESTMODE_MASK)
+#define ATW_TEST1_TESTMODE_MONITOR (0x3 <<
ATW_TEST1_TESTMODE_SHIFT)
#define ATW_TEST1_DUMP_MASK 0xf /* select dump signal
* from dxfer (huh?)
@@ -401,50 +405,52 @@
#define ATW_TEST0_BE_MASK 0xe0000000 /* Bus error state */
#define ATW_TEST0_TS_MASK 0x1c000000 /* Transmit process state */
+#define ATW_TEST0_TS_SHIFT 26
/* Stopped */
-#define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK)
+#define ATW_TEST0_TS_STOPPED (0 << ATW_TEST0_TS_SHIFT)
/* Running - fetch transmit descriptor */
-#define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK)
+#define ATW_TEST0_TS_FETCH (1 << ATW_TEST0_TS_SHIFT)
/* Running - wait for end of transmission */
-#define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK)
+#define ATW_TEST0_TS_WAIT (2 << ATW_TEST0_TS_SHIFT)
/* Running - read buffer from memory and queue into FIFO */
-#define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK)
-#define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK)
-#define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK)
+#define ATW_TEST0_TS_READING (3 << ATW_TEST0_TS_SHIFT)
+#define ATW_TEST0_TS_RESERVED1 (4 << ATW_TEST0_TS_SHIFT)
+#define ATW_TEST0_TS_RESERVED2 (5 << ATW_TEST0_TS_SHIFT)
/* Suspended */
-#define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK)
+#define ATW_TEST0_TS_SUSPENDED (6 << ATW_TEST0_TS_SHIFT)
/* Running - close transmit descriptor */
-#define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK)
+#define ATW_TEST0_TS_CLOSE (7 << ATW_TEST0_TS_SHIFT)
/* ADM8211C/CR registers */
/* Suspended */
-#define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK)
+#define ATW_C_TEST0_TS_SUSPENDED (4 << ATW_TEST0_TS_SHIFT)
/* Descriptor write */
-#define ATW_C_TEST0_TS_CLOSE LSHIFT(5, ATW_TEST0_TS_MASK)
+#define ATW_C_TEST0_TS_CLOSE (5 << ATW_TEST0_TS_SHIFT)
/* Last descriptor write */
-#define ATW_C_TEST0_TS_CLOSELAST LSHIFT(6, ATW_TEST0_TS_MASK)
+#define ATW_C_TEST0_TS_CLOSELAST (6 << ATW_TEST0_TS_SHIFT)
/* FIFO full */
-#define ATW_C_TEST0_TS_FIFOFULL LSHIFT(7, ATW_TEST0_TS_MASK)
+#define ATW_C_TEST0_TS_FIFOFULL (7 << ATW_TEST0_TS_SHIFT)
#define ATW_TEST0_RS_MASK 0x3800000 /* Receive process state */
+#define ATW_TEST0_RS_SHIFT 23
/* Stopped */
-#define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_STOPPED (0 << ATW_TEST0_RS_SHIFT)
/* Running - fetch receive descriptor */
-#define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_FETCH (1 << ATW_TEST0_RS_SHIFT)
/* Running - check for end of receive */
-#define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_CHECK (2 << ATW_TEST0_RS_SHIFT)
/* Running - wait for packet */
-#define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_WAIT (3 << ATW_TEST0_RS_SHIFT)
/* Suspended */
-#define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_SUSPENDED (4 << ATW_TEST0_RS_SHIFT)
/* Running - close receive descriptor */
-#define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_CLOSE (5 << ATW_TEST0_RS_SHIFT)
/* Running - flush current frame from FIFO */
-#define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_FLUSH (6 << ATW_TEST0_RS_SHIFT)
/* Running - queue current frame from FIFO into buffer */
-#define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK)
+#define ATW_TEST0_RS_QUEUE (7 << ATW_TEST0_RS_SHIFT)
#define ATW_TEST0_EPNE (1<<18) /* SEEPROM not detected */
#define ATW_TEST0_EPSNM (1<<17) /* SEEPROM bad
signature */
@@ -465,6 +471,7 @@
#define ATW_WCSR_BLN_MASK 0xe00000 /* lose link after BLN lost
* beacons
*/
+#define ATW_WCSR_BLN_SHIFT 21
#define ATW_WCSR_TSFTWE (1<<20) /* wake up on TSFT out
of
* range
*/
@@ -490,16 +497,21 @@
#define ATW_GPIO_LAT_MASK 0x300000 /* input latch */
#define ATW_GPIO_INTEN_MASK 0xc0000 /* interrupt enable */
#define ATW_GPIO_EN_MASK 0x3f000 /* output enable */
+#define ATW_GPIO_EN_SHIFT 12
#define ATW_GPIO_O_MASK 0xfc0 /* output value */
+#define ATW_GPIO_O_SHIFT 6
#define ATW_GPIO_I_MASK 0x3f /* pin static input */
#define ATW_BBPCTL_TWI (1<<31) /* Intersil 3-wire interface */
#define ATW_BBPCTL_RF3KADDR_MASK 0x7f000000 /* Address for RF3000 */
-#define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK)
+#define ATW_BBPCTL_RF3KADDR_SHIFT 24
+
+#define ATW_BBPCTL_RF3KADDR_ADDR (0x20 << ATW_BBPCTL_RF3KADDR_SHIFT)
#define ATW_BBPCTL_NEGEDGE_DO (1<<23) /* data-out on negative edge */
#define ATW_BBPCTL_NEGEDGE_DI (1<<22) /* data-in on negative edge */
#define ATW_BBPCTL_CCA_ACTLO (1<<21) /* CCA low when busy */
#define ATW_BBPCTL_TYPE_MASK 0x1c0000 /* BBP type */
+#define ATW_BBPCTL_TYPE_SHIFT 18
#define ATW_BBPCTL_WR (1<<17) /* start write; reset on
* completion
*/
@@ -507,7 +519,9 @@
* completion
*/
#define ATW_BBPCTL_ADDR_MASK 0xff00 /* BBP address */
+#define ATW_BBPCTL_ADDR_SHIFT 8
#define ATW_BBPCTL_DATA_MASK 0xff /* BBP data */
+#define ATW_BBPCTL_DATA_SHIFT 0
#define ATW_SYNCTL_WR (1<<31) /* start write; reset on
* completion
@@ -530,30 +544,39 @@
* edge.
*/
#define ATW_SYNCTL_RFTYPE_MASK 0x1c00000 /* RF type */
+#define ATW_SYNCTL_RFTYPE_SHIFT 22
#define ATW_SYNCTL_DATA_MASK 0x3fffff /* synthesizer setting */
#define ATW_PLCPHD_SIGNAL_MASK 0xff000000 /* signal field in PLCP header,
* only for beacon, ATIM, and
* RTS.
*/
+#define ATW_PLCPHD_SIGNAL_SHIFT 24
+
#define ATW_PLCPHD_SERVICE_MASK 0xff0000 /* service field in PLCP
* header; with RFMD BBP,
* sets Tx power for beacon,
* RTS, ATIM.
*/
+#define ATW_PLCPHD_SERVICE_SHIFT 16
#define ATW_PLCPHD_PMBL (1<<15) /* 0: long preamble, 1:
short */
#define ATW_MMIWADDR_LENLO_MASK 0xff000000 /* tx: written
4th */
+#define ATW_MMIWADDR_LENLO_SHIFT 24
#define ATW_MMIWADDR_LENHI_MASK 0xff0000 /* tx: written
3rd */
+#define ATW_MMIWADDR_LENHI_SHIFT 16
#define ATW_MMIWADDR_GAIN_MASK 0xff00 /* tx: written 2nd */
+#define ATW_MMIWADDR_GAIN_SHIFT 8
+
#define ATW_MMIWADDR_RATE_MASK 0xff /* tx: written 1st */
+#define ATW_MMIWADDR_RATE_SHIFT 0
/* was magic 0x100E0C0A */
#define ATW_MMIWADDR_INTERSIL \
- (LSHIFT(0x0c, ATW_MMIWADDR_GAIN_MASK) | \
- LSHIFT(0x0a, ATW_MMIWADDR_RATE_MASK) | \
- LSHIFT(0x0e, ATW_MMIWADDR_LENHI_MASK) | \
- LSHIFT(0x10, ATW_MMIWADDR_LENLO_MASK))
+ ((0x0c << ATW_MMIWADDR_GAIN_SHIFT) | \
+ (0x0a << ATW_MMIWADDR_RATE_SHIFT) | \
+ (0x0e << ATW_MMIWADDR_LENHI_SHIFT) | \
+ (0x10 << ATW_MMIWADDR_LENLO_SHIFT))
/* was magic 0x00009101
*
@@ -562,42 +585,46 @@
* Tx length (high) and Tx length (low) registers back-to-back.
*/
#define ATW_MMIWADDR_RFMD \
- (LSHIFT(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \
- LSHIFT(RF3000_CTL, ATW_MMIWADDR_RATE_MASK))
+ ((RF3000_TWI_AI|RF3000_GAINCTL << ATW_MMIWADDR_GAIN_SHIFT) | \
+ (RF3000_CTL << ATW_MMIWADDR_RATE_SHIFT))
#define ATW_MMIRADDR1_RSVD_MASK 0xff000000
#define ATW_MMIRADDR1_PWRLVL_MASK 0xff0000
#define ATW_MMIRADDR1_RSSI_MASK 0xff00
+#define ATW_MMIRADDR1_RSSI_SHIFT 8
#define ATW_MMIRADDR1_RXSTAT_MASK 0xff
+#define ATW_MMIRADDR1_RXSTAT_SHIFT 0
/* was magic 0x00007c7e
*
* TBD document registers for Intersil 3861 baseband
*/
#define ATW_MMIRADDR1_INTERSIL \
- (LSHIFT(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \
- LSHIFT(0x7e, ATW_MMIRADDR1_RXSTAT_MASK))
+ ((0x7c << ATW_MMIRADDR1_RSSI_SHIFT) | \
+ (0x7e << ATW_MMIRADDR1_RXSTAT_SHIFT))
/* was magic 0x00000301 */
#define ATW_MMIRADDR1_RFMD \
- (LSHIFT(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \
- LSHIFT(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK))
+ ((RF3000_RSSI << ATW_MMIRADDR1_RSSI_SHIFT) | \
+ (RF3000_RXSTAT << ATW_MMIRADDR1_RXSTAT_SHIFT))
/* was magic 0x00100000 */
#define ATW_MMIRADDR2_INTERSIL \
- (LSHIFT(0x0, ATW_MMIRADDR2_ID_MASK) | \
- LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK))
+ ((0x0 << ATW_MMIRADDR2_ID_SHIFT) | \
+ (0x10 << ATW_MMIRADDR2_RXPECNT_SHIFT))
/* was magic 0x7e100000 */
#define ATW_MMIRADDR2_RFMD \
- (LSHIFT(0x7e, ATW_MMIRADDR2_ID_MASK) | \
- LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK))
+ ((0x7e << ATW_MMIRADDR2_ID_SHIFT) | \
+ (0x10 << ATW_MMIRADDR2_RXPECNT_SHIFT))
#define ATW_MMIRADDR2_ID_MASK 0xff000000 /* 1st element ID in
WEP table
* for Probe Response (huh?)
*/
+#define ATW_MMIRADDR2_ID_SHIFT 24
/* RXPE is re-asserted after RXPECNT * 22MHz. */
#define ATW_MMIRADDR2_RXPECNT_MASK 0xff0000
+#define ATW_MMIRADDR2_RXPECNT_SHIFT 16
#define ATW_MMIRADDR2_PROREXT (1<<15) /* Probe
Response
* 11Mb/s length
* extension.
@@ -622,31 +649,39 @@
* Radio, PHYRST change after
* power-up, in 2ms units
*/
+#define ATW_TOFS2_PWR1UP_SHIFT 28
#define ATW_TOFS2_PWR0PAPE_MASK 0xf000000 /* delay of PAPE going
low
* after internal data
* transmit end, in us
*/
+#define ATW_TOFS2_PWR0PAPE_SHIFT 24
#define ATW_TOFS2_PWR1PAPE_MASK 0xf00000 /* delay of PAPE going
high
* after TXPE asserted, in us
*/
+#define ATW_TOFS2_PWR1PAPE_SHIFT 20
#define ATW_TOFS2_PWR0TRSW_MASK 0xf0000 /* delay of TRSW going low
* after internal data transmit
* end, in us
*/
+#define ATW_TOFS2_PWR0TRSW_SHIFT 16
#define ATW_TOFS2_PWR1TRSW_MASK 0xf000 /* delay of TRSW going high
* after TXPE asserted, in us
*/
+#define ATW_TOFS2_PWR1TRSW_SHIFT 12
#define ATW_TOFS2_PWR0PE2_MASK 0xf00 /* delay of PE2 going low
* after internal data transmit
* end, in us
*/
+#define ATW_TOFS2_PWR0PE2_SHIFT 8
#define ATW_TOFS2_PWR1PE2_MASK 0xf0 /* delay of PE2 going high
* after TXPE asserted, in us
*/
+#define ATW_TOFS2_PWR1PE2_SHIFT 4
#define ATW_TOFS2_PWR0TXPE_MASK 0xf /* delay of TXPE going low
* after internal data transmit
* end, in us
*/
+#define ATW_TOFS2_PWR0TXPE_SHIFT 0
#define ATW_CMDR_PM (1<<19) /* enables power mgmt
* capabilities.
@@ -656,14 +691,16 @@
*/
#define ATW_CMDR_RTE (1<<4) /* enable Rx FIFO threshold */
#define ATW_CMDR_DRT_MASK 0xc /* drain Rx FIFO threshold */
+#define ATW_CMDR_DRT_SHIFT 2
+
/* 32 bytes */
-#define ATW_CMDR_DRT_8DW LSHIFT(0x0, ATW_CMDR_DRT_MASK)
+#define ATW_CMDR_DRT_8DW (0x0 << ATW_CMDR_DRT_SHIFT)
/* 64 bytes */
-#define ATW_CMDR_DRT_16DW LSHIFT(0x1, ATW_CMDR_DRT_MASK)
+#define ATW_CMDR_DRT_16DW (0x1 << ATW_CMDR_DRT_SHIFT)
/* Store & Forward */
-#define ATW_CMDR_DRT_SF LSHIFT(0x2, ATW_CMDR_DRT_MASK)
+#define ATW_CMDR_DRT_SF (0x2 << ATW_CMDR_DRT_SHIFT)
/* Reserved */
-#define ATW_CMDR_DRT_RSVD LSHIFT(0x3, ATW_CMDR_DRT_MASK)
+#define ATW_CMDR_DRT_RSVD (0x3 << ATW_CMDR_DRT_SHIFT)
#define ATW_CMDR_SINT_MASK (1<<1) /* software interrupt---huh? */
/* TBD PCIC */
@@ -698,18 +735,26 @@
/* ATIM destination address, BSSID */
#define ATW_ABDA1_BSSIDB5_MASK 0xff000000
+#define ATW_ABDA1_BSSIDB5_SHIFT 24
#define ATW_ABDA1_BSSIDB4_MASK 0xff0000
+#define ATW_ABDA1_BSSIDB4_SHIFT 16
#define ATW_ABDA1_ATIMB5_MASK 0xff00
#define ATW_ABDA1_ATIMB4_MASK 0xff
/* BSSID */
#define ATW_BSSID0_BSSIDB3_MASK 0xff000000
+#define ATW_BSSID0_BSSIDB3_SHIFT 24
#define ATW_BSSID0_BSSIDB2_MASK 0xff0000
+#define ATW_BSSID0_BSSIDB2_SHIFT 16
#define ATW_BSSID0_BSSIDB1_MASK 0xff00
+#define ATW_BSSID0_BSSIDB1_SHIFT 8
#define ATW_BSSID0_BSSIDB0_MASK 0xff
+#define ATW_BSSID0_BSSIDB0_SHIFT 0
#define ATW_TXLMT_MTMLT_MASK 0xffff0000 /* max TX MSDU lifetime in TU */
+#define ATW_TXLMT_MTMLT_SHIFT 16
#define ATW_TXLMT_SRTYLIM_MASK 0xff /* short retry limit */
+#define ATW_TXLMT_SRTYLIM_SHIFT 0
#define ATW_MIBCNT_FFCNT_MASK 0xff000000 /* FCS failure count */
#define ATW_MIBCNT_AFCNT_MASK 0xff0000 /* ACK failure count */
@@ -719,6 +764,7 @@
#define ATW_BCNT_PLCPH_MASK 0xff0000 /* 11M PLCP length (us) */
#define ATW_BCNT_PLCPL_MASK 0xff00 /* 5.5M PLCP length (us) */
#define ATW_BCNT_BCNT_MASK 0xff /* byte count of beacon frame */
+#define ATW_BCNT_BCNT_SHIFT 0
/* For ADM8211C/CR */
/* ATW_C_TSC_TIMTABSEL = 1 */
@@ -782,9 +828,11 @@
#define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST
#define ATW_BPLI_BP_MASK 0xffff0000 /* beacon interval in TU */
-#define ATW_BPLI_LI_MASK 0xffff /* STA listen interval in
+#define ATW_BPLI_BP_SHIFT 16
+#define ATW_BPLI_LI_MASK 0xffff /* STA listen interval in
* beacon intervals
*/
+#define ATW_BPLI_LI_SHIFT 0
#define ATW_C_CAP0_TIMLEN1 0xff000000 /* TIM table 1 len in bytes
* including TIM ID (XXX huh?)
@@ -799,8 +847,10 @@
*/
#define ATW_CAP0_RCVDTIM (1<<4) /* receive every DTIM */
#define ATW_CAP0_CHN_MASK 0xf /* current DSSS channel */
+#define ATW_CAP0_CHN_SHIFT 0
#define ATW_CAP1_CAPI_MASK 0xffff0000 /* capability information */
+#define ATW_CAP1_CAPI_SHIFT 16
#define ATW_CAP1_ATIMW_MASK 0xffff /* ATIM window in TU */
#define ATW_RMD_ATIMST (1<<31) /* ATIM frame TX status */
@@ -808,12 +858,15 @@
#define ATW_RMD_PCNT 0xfff0000 /* idle time between
* awake/ps mode, in seconds
*/
-#define ATW_RMD_RMRD_MASK 0xffff /* max RX reception duration
+#define ATW_RMD_PCNT_SHIFT 16
+#define ATW_RMD_RMRD_MASK 0xffff /* max RX reception duration
* in us
*/
+#define ATW_RMD_RMRD_SHIFT 0
#define ATW_CFPP_CFPP 0xff000000 /* CFP unit DTIM */
#define ATW_CFPP_CFPMD 0xffff00 /* CFP max duration in TU */
+#define ATW_CFPP_CFPMD_SHIFT 8
#define ATW_CFPP_DTIMP 0xff /* DTIM period in beacon
* intervals
*/
@@ -821,6 +874,7 @@
* in 1 microsecond.
* Depends PCI bus speed?
*/
+#define ATW_TOFS0_USCNT_SHIFT 24
#define ATW_C_TOFS0_TUCNT_MASK 0x7c00 /* PIFS (microseconds) */
#define ATW_TOFS0_TUCNT_MASK 0x3ff /* TU counter in microseconds */
@@ -829,22 +883,31 @@
* microseconds: RF+BBP
* latency
*/
+#define ATW_TOFS1_TSFTOFSR_SHIFT 24
#define ATW_TOFS1_TBTTPRE_MASK 0xffff00 /* prediction time, (next
* Nth TBTT - TBTTOFS) in
* microseconds (huh?). To
* match TSFT[25:10] (huh?).
*/
+#define ATW_TOFS1_TBTTPRE_SHIFT 8
#define ATW_TBTTPRE_MASK 0x3fffc00
-#define ATW_TOFS1_TBTTOFS_MASK 0xff /* wake-up time offset before
+#define ATW_TOFS1_TBTTOFS_MASK 0xff /* wake-up time offset before
* TBTT in TU
*/
+#define ATW_TOFS1_TBTTOFS_SHIFT 0
#define ATW_IFST_SLOT_MASK 0xf800000 /* SLOT time in us */
+#define ATW_IFST_SLOT_SHIFT 23
#define ATW_IFST_SIFS_MASK 0x7f8000 /* SIFS time in us */
+#define ATW_IFST_SIFS_SHIFT 15
#define ATW_IFST_DIFS_MASK 0x7e00 /* DIFS time in us */
+#define ATW_IFST_DIFS_SHIFT 9
#define ATW_IFST_EIFS_MASK 0x1ff /* EIFS time in us */
+#define ATW_IFST_EIFS_SHIFT 0
#define ATW_RSPT_MART_MASK 0xffff0000 /* max response time in us */
+#define ATW_RSPT_MART_SHIFT 16
#define ATW_RSPT_MIRT_MASK 0xff00 /* min response time in us */
+#define ATW_RSPT_MIRT_SHIFT 8
#define ATW_RSPT_TSFTOFST_MASK 0xff /* TX TSFT offset in us */
#define ATW_WEPCTL_WEPENABLE (1<<31) /* enable WEP engine */
@@ -863,6 +926,7 @@
* table.
*/
#define ATW_WEPCTL_TBLADD_MASK 0x1ff /* add to table */
+#define ATW_WEPCTL_TBLADD_SHIFT 0
/* set these bits in the second byte of a SRAM shared key record to affect
* the use and interpretation of the key in the record.
@@ -871,6 +935,7 @@
#define ATW_WEP_104BIT (1<<6)
#define ATW_WESK_DATA_MASK 0xffff /* data */
+#define ATW_WESK_DATA_SHIFT 0
#define ATW_WEPCNT_WIEC_MASK 0xffff /* WEP ICV error count */
#define ATW_MACTEST_FORCE_IV (1<<23)
@@ -951,7 +1016,9 @@ struct atw_txdesc {
#define ATW_TXCTL_OWN (1<<31) /* 1: ready to transmit */
#define ATW_TXCTL_DONE (1<<30) /* 0: not processed */
#define ATW_TXCTL_TXDR_MASK 0xff00000 /* TX data rate (?) */
+#define ATW_TXCTL_TXDR_SHIFT 20
#define ATW_TXCTL_TL_MASK 0xfffff /* retry limit, 0 - 255 */
+#define ATW_TXCTL_TL_SHIFT 0
#define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */
#define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */
@@ -972,6 +1039,7 @@ struct atw_txdesc {
#define ATW_TXFLAG_TCH (1<<24) /* at_buf2 is 2nd chain */
#define ATW_TXFLAG_TBS2_MASK 0xfff000 /* at_buf2 byte count */
#define ATW_TXFLAG_TBS1_MASK 0xfff /* at_buf1 byte count */
+#define ATW_TXFLAG_TBS1_SHIFT 0
/* Rx descriptor */
struct atw_rxdesc {
@@ -987,6 +1055,7 @@ struct atw_rxdesc {
#define ATW_RXCTL_RCH (1<<24) /* ar_buf2 is 2nd chain */
#define ATW_RXCTL_RBS2_MASK 0xfff000 /* ar_buf2 byte count */
#define ATW_RXCTL_RBS1_MASK 0xfff /* ar_buf1 byte count */
+#define ATW_RXCTL_RBS1_SHIFT 0
#define ATW_RXSTAT_OWN (1<<31) /* 1: NIC may fill descriptor */
#define ATW_RXSTAT_ES (1<<30) /* error summary, 0 on
Index: atwvar.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/atwvar.h,v
retrieving revision 1.20
diff -u -p -r1.20 atwvar.h
--- atwvar.h 16 Aug 2009 18:03:48 -0000 1.20
+++ atwvar.h 16 Aug 2009 22:52:07 -0000
@@ -396,8 +396,8 @@ do {
\
__rxd->ar_buf2 = /* for descriptor chaining */ \
htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \
__rxd->ar_ctl = \
- htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \
- ATW_RXCTL_RBS1_MASK) | \
+ htole32((((__m->m_ext.ext_size - 1) & ~0x3U) << \
+ ATW_RXCTL_RBS1_SHIFT) | \
0 /* ATW_RXCTL_RCH */ | \
((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \
__rxd->ar_stat = htole32(ATW_RXSTAT_OWN); \
Index: rf3000reg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/rf3000reg.h,v
retrieving revision 1.3
diff -u -p -r1.3 rf3000reg.h
--- rf3000reg.h 16 Aug 2009 18:03:48 -0000 1.3
+++ rf3000reg.h 16 Aug 2009 22:52:07 -0000
@@ -68,6 +68,7 @@
#define RF3000_CCACTL 0x02 /* CCA control */
/* CCA mode */
#define RF3000_CCACTL_MODE_MASK 0xc0
+#define RF3000_CCACTL_MODE_SHIFT 6
#define RF3000_CCACTL_MODE_RSSIT 0 /* RSSI
threshold */
#define RF3000_CCACTL_MODE_ACQ 1 /* acquisition
*/
#define RF3000_CCACTL_MODE_BOTH 2 /* threshold or
acq. */
@@ -82,9 +83,11 @@
#define RF3000_RSSI_MASK 0x3f
#define RF3000_GAINCTL 0x11 /* TX variable gain control */
#define RF3000_GAINCTL_TXVGC_MASK 0xfc
+#define RF3000_GAINCTL_TXVGC_SHIFT 2
#define RF3000_GAINCTL_SCRAMBLER (1<<1)
#define RF3000_LOGAINCAL 0x14 /* low gain calibration
*/
#define RF3000_LOGAINCAL_CAL_MASK 0x3f
+#define RF3000_LOGAINCAL_CAL_SHIFT 0
#define RF3000_HIGAINCAL 0x15 /* high gain
calibration */
#define RF3000_HIGAINCAL_CAL_MASK 0x3f
#define RF3000_HIGAINCAL_DSSSPAD (1<<6) /* 6dB gain pad
for DSSS
Index: si4136reg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/si4136reg.h,v
retrieving revision 1.3
diff -u -p -r1.3 si4136reg.h
--- si4136reg.h 16 Aug 2009 18:03:48 -0000 1.3
+++ si4136reg.h 16 Aug 2009 22:52:07 -0000
@@ -39,7 +39,9 @@
* Serial bus format for Silicon Laboratories Si4126/Si4136 RF synthesizer.
*/
#define SI4126_TWI_DATA_MASK 0x3ffff0
+#define SI4126_TWI_DATA_SHIFT 4
#define SI4126_TWI_ADDR_MASK 0xf
+#define SI4126_TWI_ADDR_SHIFT 0
/*
* Registers for Silicon Laboratories Si4126/Si4136 RF synthesizer.
@@ -71,6 +73,7 @@
#define SI4126_GAIN 1 /* phase detector gain */
#define SI4126_GAIN_KPI_MASK 0x30 /* IF phase detector gain */
#define SI4126_GAIN_KP2_MASK 0xc /* RF2 phase detector gain */
+#define SI4126_GAIN_KP2_SHIFT 2
#define SI4126_GAIN_KP1_MASK 0x3 /* RF1 phase detector gain */
#define SI4126_POWER 2 /* powerdown */
