Oops, try again... At Tue, 09 Nov 2010 20:48:37 +0900, SASANO Takayoshi wrote: > > Hello, > > Phenom 9500 has TLB errata and this should be workarounded by BIOS. > But some BIOS do nothing by default, I think the warning is needed. > > Here is the patch, please review. > > -- > amd64errata.c > - applied following NetBSD's src/sys/arch/x86/x86/errata.c fix > revision 1.8, 1.13, 1.17 and 1.18 > > specialreg.h > - add definitions for amd64errata.c > - modified NB_CFG_DISIOREQLOCK and DC_CFG_DIS_CNV_WC_SSO, > they are misdefined (see src/sys/arch/x86/include/specialreg.h > of NetBSD, revision 1.48 and 1.49) > -- > SASANO Takayoshi (JG1UAA/@uaa) [http://www.uaa.org.uk] <u...@uaa.org.uk> > > [demime 1.01d removed an attachment of type application/octet-stream] >
---- Index: arch/amd64/amd64/amd64errata.c =================================================================== RCS file: /cvs/src/sys/arch/amd64/amd64/amd64errata.c,v retrieving revision 1.2 diff -u -p -r1.2 amd64errata.c --- arch/amd64/amd64/amd64errata.c 26 Jun 2008 05:42:09 -0000 1.2 +++ arch/amd64/amd64/amd64errata.c 9 Nov 2010 11:45:32 -0000 @@ -64,6 +64,7 @@ typedef struct errata { typedef enum cpurev { BH_E4, CH_CG, CH_D0, DH_CG, DH_D0, DH_E3, DH_E6, JH_E1, JH_E6, SH_B0, SH_B3, SH_C0, SH_CG, SH_D0, SH_E4, SH_E5, + DR_BA, DR_B2, DR_B3, OINK } cpurev_t; @@ -78,6 +79,7 @@ static const u_int cpurevs[] = { SH_CG, 0x0000f4a, SH_CG, 0x0000f5a, SH_CG, 0x0000f7a, SH_D0, 0x0010f40, SH_D0, 0x0010f50, SH_D0, 0x0010f70, SH_E4, 0x0020f51, SH_E4, 0x0020f71, SH_E5, 0x0020f42, + DR_BA, 0x0100f2a, DR_B2, 0x0100f22, DR_B3, 0x0100f23, OINK }; @@ -117,6 +119,14 @@ static const uint8_t amd64_errata_set8[] SH_D0, SH_D0, SH_D0, SH_E4, SH_E4, SH_E5, OINK }; +static const uint8_t amd64_errata_set9[] = { + DR_BA, DR_B2, OINK +}; + +static const uint8_t amd64_errata_set10[] = { + DR_BA, DR_B2, DR_B3, OINK +}; + static int amd64_errata_setmsr(struct cpu_info *, errata_t *); static int amd64_errata_testmsr(struct cpu_info *, errata_t *); @@ -178,7 +188,6 @@ static errata_t errata[] = { 113, 0, MSR_BU_CFG, amd64_errata_set3, amd64_errata_setmsr, BU_CFG_WBENHWSBDIS }, -#ifdef MULTIPROCESSOR /* * 69: Multiprocessor Coherency Problem with Hardware * Prefetch Mechanism @@ -211,7 +220,6 @@ static errata_t errata[] = { 107, 0, MSR_BU_CFG, amd64_errata_set2, amd64_errata_testmsr, BU_CFG_THRL2IDXCMPDIS }, -#if 0 /* * 122: TLB Flush Filter May Cause Coherency Problem in * Multiprocessor Systems @@ -220,8 +228,41 @@ static errata_t errata[] = { 122, 0, MSR_HWCR, amd64_errata_set4, amd64_errata_setmsr, HWCR_FFDIS }, -#endif -#endif /* MULTIPROCESSOR */ + /* + * 254: Internal Resource Livelock Involving Cached TLB Reload + */ + { + 254, 0, MSR_BU_CFG, amd64_errata_set9, + amd64_errata_testmsr, BU_CFG_ERRATA_254 + }, + /* + * 261: Processor May Stall Entering Stop-Grant Due to Pending Data + * Cache Scrub + */ + { + 261, 0, MSR_DC_CFG, amd64_errata_set10, + amd64_errata_testmsr, DC_CFG_ERRATA_261 + }, + /* + * 298: L2 Eviction May Occur During Processor Operation To Set + * Accessed or Dirty Bit + */ + { + 298, 0, MSR_HWCR, amd64_errata_set9, + amd64_errata_testmsr, HWCR_TLBCACHEDIS + }, + { + 298, 0, MSR_BU_CFG, amd64_errata_set9, + amd64_errata_testmsr, BU_CFG_ERRATA_298 + }, + /* + * 309: Processor Core May Execute Incorrect Instructions on + * Concurrent L2 and Northbridge Response + */ + { + 309, 0, MSR_BU_CFG, amd64_errata_set9, + amd64_errata_testmsr, BU_CFG_ERRATA_309 + }, }; static int Index: arch/amd64/include/specialreg.h =================================================================== RCS file: /cvs/src/sys/arch/amd64/include/specialreg.h,v retrieving revision 1.19 diff -u -p -r1.19 specialreg.h --- arch/amd64/include/specialreg.h 29 Apr 2010 17:00:48 -0000 1.19 +++ arch/amd64/include/specialreg.h 9 Nov 2010 11:45:32 -0000 @@ -316,11 +316,13 @@ * These require a 'passcode' for access. See cpufunc.h. */ #define MSR_HWCR 0xc0010015 +#define HWCR_TLBCACHEDIS 0x00000008 #define HWCR_FFDIS 0x00000040 #define MSR_NB_CFG 0xc001001f -#define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL +#define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL #define NB_CFG_DISDATMSK 0x0000001000000000ULL +#define NB_CFG_INITAPICCPUIDLO (1ULL << 54) #define MSR_LS_CFG 0xc0011020 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 @@ -329,10 +331,14 @@ #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 #define MSR_DC_CFG 0xc0011022 -#define DC_CFG_DIS_CNV_WC_SSO 0x00000004 +#define DC_CFG_DIS_CNV_WC_SSO 0x00000008 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 +#define DC_CFG_ERRATA_261 0x01000000 #define MSR_BU_CFG 0xc0011023 +#define BU_CFG_ERRATA_298 0x0000000000000002ULL +#define BU_CFG_ERRATA_254 0x0000000000200000ULL +#define BU_CFG_ERRATA_309 0x0000000000800000ULL #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL