I've been running this for a few months without any problems.
Brad
mskc0 at pci2 dev 0 function 0 "Marvell Yukon 88E8056" rev 0x20, Yukon-2
EC Ultra rev. B0 (0x3): apic 4 int 19 (irq 10)
msk0 at mskc0 port A: address 00:1c:25:57:71:1f
eephy0 at msk0 phy 0: 88E1149 Gigabit PHY, rev. 1
Index: sys/dev/pci/if_skreg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_skreg.h,v
retrieving revision 1.55
diff -u sys/dev/pci/if_skreg.h
--- sys/dev/pci/if_skreg.h 17 Nov 2010 13:19:39 -0000 1.55
+++ sys/dev/pci/if_skreg.h 17 Feb 2012 17:35:47 -0000
@@ -1475,11 +1475,26 @@
#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */
#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */
#define SK_PCI_PME_EVENT 0x004F
+#define SK_PCI_OURREG3 0x0080 /* Yukon EC U */
+#define SK_PCI_OURREG4 0x0084
+#define SK_PCI_OURREG5 0x0088
#define SK_Y2_REG1_PHY1_PWRD 0x04000000
#define SK_Y2_REG1_PHY2_PWRD 0x08000000
#define SK_Y2_REG1_PHY1_COMA 0x10000000
#define SK_Y2_REG1_PHY2_COMA 0x20000000
+
+/* SK_PCI_OURREG4 32bits (Yukon-ECU only) */
+#define SK_Y2_REG4_TIMER_VALUE_MSK (0xff << 16)
+#define SK_Y2_REG4_FORCE_ASPM_REQUEST 0x8000 //__BIT(15)
+#define SK_Y2_REG4_ASPM_GPHY_LINK_DOWN 0x4000 //__BIT(14)
+#define SK_Y2_REG4_ASPM_INT_FIFO_EMPTY 0x2000 //__BIT(13)
+#define SK_Y2_REG4_ASPM_CLKRUN_REQUEST 0x1000 //__BIT(12)
+#define SK_Y2_REG4_ASPM_FORCE_CLKREQ_ENA 0x10 //__BIT(4)
+#define SK_Y2_REG4_ASPM_CLKREQ_PAD 0x08 //__BIT(3)
+#define SK_Y2_REG4_ASPM_A1_MODE_SELECT 0x04 //__BIT(2)
+#define SK_Y2_REG4_CLK_GATE_PEX_UNIT_ENA 0x02 //__BIT(1)
+#define SK_Y2_REG4_CLK_GATE_ROOT_COR_ENA 0x01 //__BIT(0)
#define SK_PSTATE_MASK 0x0003
#define SK_PSTATE_D0 0x0000
Index: sys/dev/pci/if_msk.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_msk.c,v
retrieving revision 1.93
diff -u sys/dev/pci/if_msk.c
--- sys/dev/pci/if_msk.c 22 Jun 2011 16:44:27 -0000 1.93
+++ sys/dev/pci/if_msk.c 17 Feb 2012 17:35:46 -0000
@@ -694,6 +694,29 @@
reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
else
reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
+
+ if (sc->sk_type == SK_YUKON_EC_U) {
+ uint32_t our;
+
+#if 0
+ CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON);
+#endif
+
+ /* enable all clocks. */
+ sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0);
+ our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4));
+ our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST|
+ SK_Y2_REG4_ASPM_GPHY_LINK_DOWN|
+ SK_Y2_REG4_ASPM_INT_FIFO_EMPTY|
+ SK_Y2_REG4_ASPM_CLKRUN_REQUEST);
+ /* Set all bits to 0 except bits 15..12 */
+ sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our);
+ /* Set to default value */
+ sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0);
+ }
+
+ /* release PHY from PowerDown/Coma mode. */
+
sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
