The following diff makes the bus_clock calculations
happen later in the boot process so the speedstep
code can use it as a fallback in future instead of
having it called unconditionally.
Index: i386/est.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/est.c,v
retrieving revision 1.37
diff -u -p -r1.37 est.c
--- i386/est.c 13 May 2011 11:30:26 -0000 1.37
+++ i386/est.c 24 Mar 2012 05:32:12 -0000
@@ -960,6 +960,10 @@ static struct fqlist *est_fqlist;
extern int setperf_prio;
extern int perflevel;
+void p4_get_bus_clock(struct cpu_info *);
+void p3_get_bus_clock(struct cpu_info *);
+void cyrix3_get_bus_clock(struct cpu_info *);
+
#if NACPICPU > 0
struct fqlist * est_acpi_init(void);
void est_acpi_pss_changed(struct acpicpu_pss *, int);
@@ -1044,8 +1048,9 @@ est_acpi_pss_changed(struct acpicpu_pss
#endif
void
-est_init(const char *cpu_device, int vendor)
+est_init(struct cpu_info *ci, int vendor)
{
+ const char *cpu_device = ci->ci_dev.dv_xname;
int i, low, high;
u_int64_t msr;
u_int16_t idhi, idlo, cur;
@@ -1071,6 +1076,13 @@ est_init(const char *cpu_device, int ven
#if NACPICPU > 0
est_fqlist = est_acpi_init();
#endif
+
+ if (vendor == CPUVENDOR_VIA)
+ cyrix3_get_bus_clock(ci);
+ else if (ci->ci_family == 0xf)
+ p4_get_bus_clock(ci);
+ else if (ci->ci_family == 6)
+ p3_get_bus_clock(ci);
/*
* Interpreting the values of PERF_STATUS is not valid
Index: i386/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.508
diff -u -p -r1.508 machdep.c
--- i386/machdep.c 23 Mar 2012 15:51:25 -0000 1.508
+++ i386/machdep.c 24 Mar 2012 05:32:13 -0000
@@ -1053,7 +1053,7 @@ cyrix3_setperf_setup(struct cpu_info *ci
{
if (cpu_ecxfeature & CPUIDECX_EST) {
if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
- est_init(ci->ci_dev.dv_xname, CPUVENDOR_VIA);
+ est_init(ci, CPUVENDOR_VIA);
else
printf("%s: Enhanced SpeedStep disabled by BIOS\n",
ci->ci_dev.dv_xname);
@@ -1076,8 +1076,6 @@ cyrix3_cpu_setup(struct cpu_info *ci)
pagezero = i686_pagezero;
- cyrix3_get_bus_clock(ci);
-
setperf_setup = cyrix3_setperf_setup;
#endif
@@ -1443,7 +1441,7 @@ intel686_setperf_setup(struct cpu_info *
if (cpu_ecxfeature & CPUIDECX_EST) {
if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
- est_init(ci->ci_dev.dv_xname, CPUVENDOR_INTEL);
+ est_init(ci, CPUVENDOR_INTEL);
else
printf("%s: Enhanced SpeedStep disabled by BIOS\n",
ci->ci_dev.dv_xname);
@@ -1485,10 +1483,6 @@ intel686_cpu_setup(struct cpu_info *ci)
int step = ci->ci_signature & 15;
u_quad_t msr119;
-#if !defined(SMALL_KERNEL)
- p3_get_bus_clock(ci);
-#endif
-
intel686_common_cpu_setup(ci);
/*
@@ -1521,10 +1515,6 @@ intel686_cpu_setup(struct cpu_info *ci)
void
intel686_p4_cpu_setup(struct cpu_info *ci)
{
-#if !defined(SMALL_KERNEL)
- p4_get_bus_clock(ci);
-#endif
-
intel686_common_cpu_setup(ci);
#if !defined(SMALL_KERNEL)
@@ -2156,9 +2146,13 @@ print_msr:
void
p4_update_cpuspeed(void)
{
+ struct cpu_info *ci;
u_int64_t msr;
int mult;
+ ci = curcpu();
+ p4_get_bus_clock(ci);
+
if (bus_clock == 0) {
printf("p4_update_cpuspeed: unknown bus clock\n");
return;
@@ -2173,10 +2167,14 @@ p4_update_cpuspeed(void)
void
p3_update_cpuspeed(void)
{
+ struct cpu_info *ci;
u_int64_t msr;
int mult;
const u_int8_t mult_code[] = {
50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 };
+
+ ci = curcpu();
+ p3_get_bus_clock(ci);
if (bus_clock == 0) {
printf("p3_update_cpuspeed: unknown bus clock\n");
Index: include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/i386/include/cpu.h,v
retrieving revision 1.121
diff -u -p -r1.121 cpu.h
--- include/cpu.h 2 Nov 2011 23:53:44 -0000 1.121
+++ include/cpu.h 24 Mar 2012 05:32:13 -0000
@@ -388,7 +388,7 @@ void i8254_inittimecounter_simple(void);
#if !defined(SMALL_KERNEL)
/* est.c */
-void est_init(const char *, int);
+void est_init(struct cpu_info *, int);
void est_setperf(int);
/* longrun.c */
void longrun_init(void);
