> Date: Wed, 15 Aug 2012 16:31:53 +0200 > From: Antoine Jacoutot <[email protected]> > > On Sun, Aug 12, 2012 at 01:22:55PM +1000, David Gwynne wrote: > > ive been beating my head against why mpi is slow on some machines > > and not others, and i think this may be why. > > > > issuing a command to the chip is done by posting its address to a > > register. in my code this was done by doing a write to the register > > and then using a barrier immediately after. i think the barrier > > causes the cpu to wait till it knows the memory is flushed to the > > register, when in reality we dont care when it happens, we should > > go do other more important things. > > > > ive only done basic testing so far, but i am hopeful. > > Working fine on my sparc64 t2K. > I haven't noticed any performance improvements yet but it is stable so far. > > I was hoping this would fix my softdep issue on this machine (when > softdep is on, the max throughput become 2M/s or so ...).
The buffer cache is still broken!
