Hi. Is there any progress/comments on this?
On Fri, Sep 28, 2012 at 11:29 PM, Alexey Suslikov <[email protected]> wrote: > Hi. > > With input from tedu@, guenther@ and others, below are: > 1) test case; > 2) backtrace for test case; > 3) locking diff; > 4) dmesg (amd64 GENERIC.MP built from 2012-09-28 CVS). > > Diff introduces no changes to srandomdev(): correct me if I'm wrong, > but no mutex can be used since sysctl can sleep. > > Rebuild and reinstall in src/lib/librthread and src/lib/libc after applying > the diff. > > Expect test case (and Kannel port of course) not crashing after rebuild > and reinstall. > > Cheers, > Alexey > > 1) test case. > > #include <pthread.h> > #include <stdio.h> > #include <stdlib.h> > #include <assert.h> > #include <unistd.h> > > #define NUM_THREADS 1800 > > void *TaskCode(void *argument) > { > struct timeval tv; > > gettimeofday(&tv, 0); > srandom((getpid() << 16) ^ getuid() ^ tv.tv_sec ^ tv.tv_usec); > > return NULL; > } > > int main(void) > { > pthread_t threads[NUM_THREADS]; > int thread_args[NUM_THREADS]; > int rc, i; > > /* create all threads */ > for (i=0; i<NUM_THREADS; ++i) { > thread_args[i] = i; > rc = pthread_create(&threads[i], NULL, TaskCode, (void *) > &thread_args[i]); > assert(0 == rc); > } > > /* wait for all threads to complete */ > for (i=0; i<NUM_THREADS; ++i) { > rc = pthread_join(threads[i], NULL); > assert(0 == rc); > } > > printf("Test srandom success\n"); > exit(EXIT_SUCCESS); > } > > 2) backtrace for test case. > > Program received signal SIGSEGV, Segmentation fault. > [Switching to thread 1030380] > 0x000019d34d618f8e in random () at /usr/src/lib/libc/stdlib/random.c:387 > 387 *fptr += *rptr; > > (gdb) bt > #0 0x000019d34d618f8e in random () at /usr/src/lib/libc/stdlib/random.c:387 > #1 0x000019d34d619169 in srandom (x=Variable "x" is not available. > ) at /usr/src/lib/libc/stdlib/random.c:216 > #2 0x000019d140000fe1 in TaskCode (argument=0x7f7ffffea004) at > test_srandom.c:14 > #3 0x000019d34999d11e in _rthread_start (v=Variable "v" is not available. > ) at /usr/src/lib/librthread/rthread.c:122 > #4 0x000019d34d5f0f9b in __tfork_thread () at > /usr/src/lib/libc/arch/amd64/sys/tfork_thread.S:75 > Cannot access memory at address 0x19d344efb000 > > 3) locking diff. > > Index: lib/libc/include/thread_private.h > =================================================================== > RCS file: /cvs/src/lib/libc/include/thread_private.h,v > retrieving revision 1.25 > diff -u -p -r1.25 thread_private.h > --- lib/libc/include/thread_private.h 16 Oct 2011 06:29:56 -0000 1.25 > +++ lib/libc/include/thread_private.h 27 Sep 2012 10:48:45 -0000 > @@ -172,4 +172,16 @@ void _thread_arc4_unlock(void); > _thread_arc4_unlock();\ > } while (0) > > +void _thread_random_lock(void); > +void _thread_random_unlock(void); > + > +#define _RANDOM_LOCK() do { \ > + if (__isthreaded) \ > + _thread_random_lock(); \ > + } while (0) > +#define _RANDOM_UNLOCK() do { \ > + if (__isthreaded) \ > + _thread_random_unlock();\ > + } while (0) > + > #endif /* _THREAD_PRIVATE_H_ */ > Index: lib/libc/stdlib/random.c > =================================================================== > RCS file: /cvs/src/lib/libc/stdlib/random.c,v > retrieving revision 1.17 > diff -u -p -r1.17 random.c > --- lib/libc/stdlib/random.c 1 Jun 2012 01:01:57 -0000 1.17 > +++ lib/libc/stdlib/random.c 27 Sep 2012 10:48:45 -0000 > @@ -35,6 +35,10 @@ > #include <stdio.h> > #include <stdlib.h> > #include <unistd.h> > +#include "thread_private.h" > + > +static void srandom_unlocked(unsigned int); > +static long random_unlocked(void); > > /* > * random.c: > @@ -186,8 +190,8 @@ static int rand_sep = SEP_3; > * introduced by the L.C.R.N.G. Note that the initialization of randtbl[] > * for default usage relies on values produced by this routine. > */ > -void > -srandom(unsigned int x) > +static void > +srandom_unlocked(unsigned int x) > { > int i; > int32_t test; > @@ -213,10 +217,18 @@ srandom(unsigned int x) > fptr = &state[rand_sep]; > rptr = &state[0]; > for (i = 0; i < 10 * rand_deg; i++) > - (void)random(); > + (void)random_unlocked(); > } > } > > +void > +srandom(unsigned int x) > +{ > + _RANDOM_LOCK(); > + srandom_unlocked(x); > + _RANDOM_UNLOCK(); > +} > + > /* > * srandomdev: > * > @@ -273,12 +285,15 @@ initstate(u_int seed, char *arg_state, s > { > char *ostate = (char *)(&state[-1]); > > + _RANDOM_LOCK(); > if (rand_type == TYPE_0) > state[-1] = rand_type; > else > state[-1] = MAX_TYPES * (rptr - state) + rand_type; > - if (n < BREAK_0) > + if (n < BREAK_0) { > + _RANDOM_UNLOCK(); > return(NULL); > + } > if (n < BREAK_1) { > rand_type = TYPE_0; > rand_deg = DEG_0; > @@ -302,11 +317,12 @@ initstate(u_int seed, char *arg_state, s > } > state = &(((int32_t *)arg_state)[1]); /* first location */ > end_ptr = &state[rand_deg]; /* must set end_ptr before srandom */ > - srandom(seed); > + srandom_unlocked(seed); > if (rand_type == TYPE_0) > state[-1] = rand_type; > else > state[-1] = MAX_TYPES*(rptr - state) + rand_type; > + _RANDOM_UNLOCK(); > return(ostate); > } > > @@ -333,6 +349,7 @@ setstate(char *arg_state) > int32_t rear = new_state[0] / MAX_TYPES; > char *ostate = (char *)(&state[-1]); > > + _RANDOM_LOCK(); > if (rand_type == TYPE_0) > state[-1] = rand_type; > else > @@ -348,6 +365,7 @@ setstate(char *arg_state) > rand_sep = seps[type]; > break; > default: > + _RANDOM_UNLOCK(); > return(NULL); > } > state = &new_state[1]; > @@ -356,6 +374,7 @@ setstate(char *arg_state) > fptr = &state[(rear + rand_sep) % rand_deg]; > } > end_ptr = &state[rand_deg]; /* set end_ptr too */ > + _RANDOM_UNLOCK(); > return(ostate); > } > > @@ -376,8 +395,8 @@ setstate(char *arg_state) > * > * Returns a 31-bit random number. > */ > -long > -random(void) > +static long > +random_unlocked(void) > { > int32_t i; > > @@ -393,4 +412,15 @@ random(void) > rptr = state; > } > return((long)i); > +} > + > +long > +random(void) > +{ > + long r; > + > + _RANDOM_LOCK(); > + r = random_unlocked(); > + _RANDOM_UNLOCK(); > + return (r); > } > Index: lib/libc/thread/unithread_malloc_lock.c > =================================================================== > RCS file: /cvs/src/lib/libc/thread/unithread_malloc_lock.c,v > retrieving revision 1.8 > diff -u -p -r1.8 unithread_malloc_lock.c > --- lib/libc/thread/unithread_malloc_lock.c 13 Jun 2008 21:18:43 -0000 > 1.8 > +++ lib/libc/thread/unithread_malloc_lock.c 27 Sep 2012 10:48:46 -0000 > @@ -21,6 +21,12 @@ WEAK_PROTOTYPE(_thread_arc4_unlock); > WEAK_ALIAS(_thread_arc4_lock); > WEAK_ALIAS(_thread_arc4_unlock); > > +WEAK_PROTOTYPE(_thread_random_lock); > +WEAK_PROTOTYPE(_thread_random_unlock); > + > +WEAK_ALIAS(_thread_random_lock); > +WEAK_ALIAS(_thread_random_unlock); > + > void > WEAK_NAME(_thread_malloc_lock)(void) > { > @@ -53,6 +59,18 @@ WEAK_NAME(_thread_arc4_lock)(void) > > void > WEAK_NAME(_thread_arc4_unlock)(void) > +{ > + return; > +} > + > +void > +WEAK_NAME(_thread_random_lock)(void) > +{ > + return; > +} > + > +void > +WEAK_NAME(_thread_random_unlock)(void) > { > return; > } > Index: lib/librthread/rthread.c > =================================================================== > RCS file: /cvs/src/lib/librthread/rthread.c,v > retrieving revision 1.66 > diff -u -p -r1.66 rthread.c > --- lib/librthread/rthread.c 22 Aug 2012 23:43:32 -0000 1.66 > +++ lib/librthread/rthread.c 27 Sep 2012 10:48:46 -0000 > @@ -674,6 +674,8 @@ static void *__libc_overrides[] __used = > &__errno, > &_thread_arc4_lock, > &_thread_arc4_unlock, > + &_thread_random_lock, > + &_thread_random_unlock, > &_thread_atexit_lock, > &_thread_atexit_unlock, > &_thread_malloc_lock, > Index: lib/librthread/rthread_fork.c > =================================================================== > RCS file: /cvs/src/lib/librthread/rthread_fork.c,v > retrieving revision 1.6 > diff -u -p -r1.6 rthread_fork.c > --- lib/librthread/rthread_fork.c 22 Aug 2012 23:43:32 -0000 1.6 > +++ lib/librthread/rthread_fork.c 27 Sep 2012 10:48:46 -0000 > @@ -91,6 +91,7 @@ _dofork(int is_vfork) > _thread_atexit_lock(); > _thread_malloc_lock(); > _thread_arc4_lock(); > + _thread_random_lock(); > > #if defined(__ELF__) > if (_DYNAMIC) > @@ -107,6 +108,7 @@ _dofork(int is_vfork) > _thread_arc4_unlock(); > _thread_malloc_unlock(); > _thread_atexit_unlock(); > + _thread_random_unlock(); > > #if defined(__ELF__) > if (_DYNAMIC) > Index: lib/librthread/rthread_libc.c > =================================================================== > RCS file: /cvs/src/lib/librthread/rthread_libc.c,v > retrieving revision 1.10 > diff -u -p -r1.10 rthread_libc.c > --- lib/librthread/rthread_libc.c 17 Apr 2012 15:10:11 -0000 1.10 > +++ lib/librthread/rthread_libc.c 27 Sep 2012 10:48:46 -0000 > @@ -200,3 +200,19 @@ _thread_arc4_unlock(void) > _spinunlock(&arc4_lock); > } > > +/* > + * random lock > + */ > +static _spinlock_lock_t random_lock = _SPINLOCK_UNLOCKED; > + > +void > +_thread_random_lock(void) > +{ > + _spinlock(&random_lock); > +} > + > +void > +_thread_random_unlock(void) > +{ > + _spinunlock(&random_lock); > +} > > 4) dmesg. > > OpenBSD 5.2-current (GENERIC.MP) #0: Fri Sep 28 20:27:53 EEST 2012 > ***@***:/usr/src/sys/arch/amd64/compile/GENERIC.MP > real mem = 8580038656 (8182MB) > avail mem = 8329166848 (7943MB) > mainbus0 at root > bios0 at mainbus0: SMBIOS rev. 2.6 @ 0x9f000 (68 entries) > bios0: vendor American Megatrends Inc. version "1.1" date 05/27/2010 > bios0: Supermicro X8SIL > acpi0 at bios0: rev 2 > acpi0: sleep states S0 S1 S4 S5 > acpi0: tables DSDT FACP APIC MCFG OEMB HPET GSCI SSDT EINJ BERT ERST HEST > acpi0: wakeup devices P0P1(S4) P0P3(S4) P0P4(S4) P0P5(S4) P0P6(S4) > BR1E(S4) PS2K(S4) PS2M(S4) USB0(S4) USB1(S4) USB2(S4) USB3(S4) > USB4(S4) USB5(S4) USB6(S4) GBE_(S4) BR20(S4) BR21(S4) BR22(S4) > BR23(S4) BR24(S4) BR25(S4) BR26(S4) BR27(S4) EUSB(S4) USBE(S4) > SLPB(S4) > acpitimer0 at acpi0: 3579545 Hz, 24 bits > acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat > cpu0 at mainbus0: apid 0 (boot processor) > cpu0: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.66 MHz > cpu0: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu0: 256KB 64b/line 8-way L2 cache > cpu0: apic clock running at 133MHz > cpu1 at mainbus0: apid 2 (application processor) > cpu1: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.33 MHz > cpu1: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu1: 256KB 64b/line 8-way L2 cache > cpu2 at mainbus0: apid 4 (application processor) > cpu2: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.33 MHz > cpu2: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu2: 256KB 64b/line 8-way L2 cache > cpu3 at mainbus0: apid 6 (application processor) > cpu3: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.33 MHz > cpu3: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu3: 256KB 64b/line 8-way L2 cache > cpu4 at mainbus0: apid 1 (application processor) > cpu4: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.33 MHz > cpu4: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu4: 256KB 64b/line 8-way L2 cache > cpu5 at mainbus0: apid 3 (application processor) > cpu5: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.33 MHz > cpu5: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu5: 256KB 64b/line 8-way L2 cache > cpu6 at mainbus0: apid 5 (application processor) > cpu6: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.33 MHz > cpu6: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu6: 256KB 64b/line 8-way L2 cache > cpu7 at mainbus0: apid 7 (application processor) > cpu7: Intel(R) Xeon(R) CPU X3440 @ 2.53GHz, 2533.33 MHz > cpu7: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,NXE,LONG,LAHF > cpu7: 256KB 64b/line 8-way L2 cache > ioapic0 at mainbus0: apid 8 pa 0xfec00000, version 20, 24 pins > ioapic0: misconfigured as apic 1, remapped to apid 8 > acpimcfg0 at acpi0 addr 0xe0000000, bus 0-255 > acpihpet0 at acpi0: 14318179 Hz > acpiprt0 at acpi0: bus 0 (PCI0) > acpiprt1 at acpi0: bus -1 (P0P1) > acpiprt2 at acpi0: bus 1 (P0P3) > acpiprt3 at acpi0: bus 2 (P0P5) > acpiprt4 at acpi0: bus -1 (P0P6) > acpiprt5 at acpi0: bus 6 (BR1E) > acpiprt6 at acpi0: bus 3 (BR20) > acpiprt7 at acpi0: bus 4 (BR24) > acpiprt8 at acpi0: bus 5 (BR25) > acpicpu0 at acpi0: C3, C2, C1, PSS > acpicpu1 at acpi0: C3, C2, C1, PSS > acpicpu2 at acpi0: C3, C2, C1, PSS > acpicpu3 at acpi0: C3, C2, C1, PSS > acpicpu4 at acpi0: C3, C2, C1, PSS > acpicpu5 at acpi0: C3, C2, C1, PSS > acpicpu6 at acpi0: C3, C2, C1, PSS > acpicpu7 at acpi0: C3, C2, C1, PSS > acpibtn0 at acpi0: SLPB > acpibtn1 at acpi0: PWRB > ipmi at mainbus0 not configured > cpu0: Enhanced SpeedStep 2533 MHz: speeds: 2534, 2533, 2400, 2267, > 2133, 2000, 1867, 1733, 1600, 1467, 1333, 1200 MHz > pci0 at mainbus0 bus 0 > pchb0 at pci0 dev 0 function 0 "Intel Core DMI" rev 0x11 > ppb0 at pci0 dev 3 function 0 "Intel Core PCIE" rev 0x11: msi > pci1 at ppb0 bus 1 > ppb1 at pci0 dev 5 function 0 "Intel Core PCIE" rev 0x11: msi > pci2 at ppb1 bus 2 > "Intel Core Management" rev 0x11 at pci0 dev 8 function 0 not configured > "Intel Core Scratch" rev 0x11 at pci0 dev 8 function 1 not configured > "Intel Core Control" rev 0x11 at pci0 dev 8 function 2 not configured > "Intel Core Misc" rev 0x11 at pci0 dev 8 function 3 not configured > "Intel Core QPI Link" rev 0x11 at pci0 dev 16 function 0 not configured > "Intel Core QPI Routing" rev 0x11 at pci0 dev 16 function 1 not configured > ehci0 at pci0 dev 26 function 0 "Intel 3400 USB" rev 0x05: apic 8 int 21 > usb0 at ehci0: USB revision 2.0 > uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1 > ppb2 at pci0 dev 28 function 0 "Intel 3400 PCIE" rev 0x05: msi > pci3 at ppb2 bus 3 > ppb3 at pci0 dev 28 function 4 "Intel 3400 PCIE" rev 0x05: msi > pci4 at ppb3 bus 4 > em0 at pci4 dev 0 function 0 "Intel PRO/1000 MT (82574L)" rev 0x00: > msi, address 00:25:90:34:c5:aa > ppb4 at pci0 dev 28 function 5 "Intel 3400 PCIE" rev 0x05: msi > pci5 at ppb4 bus 5 > em1 at pci5 dev 0 function 0 "Intel PRO/1000 MT (82574L)" rev 0x00: > msi, address 00:25:90:34:c5:ab > ehci1 at pci0 dev 29 function 0 "Intel 3400 USB" rev 0x05: apic 8 int 23 > usb1 at ehci1: USB revision 2.0 > uhub1 at usb1 "Intel EHCI root hub" rev 2.00/1.00 addr 1 > ppb5 at pci0 dev 30 function 0 "Intel 82801BA Hub-to-PCI" rev 0xa5 > pci6 at ppb5 bus 6 > vga1 at pci6 dev 3 function 0 "Matrox MGA G200eW" rev 0x0a > wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation) > wsdisplay0: screen 1-5 added (80x25, vt100 emulation) > pcib0 at pci0 dev 31 function 0 "Intel 3420 LPC" rev 0x05 > ahci0 at pci0 dev 31 function 2 "Intel 3400 AHCI" rev 0x05: msi, AHCI 1.3 > scsibus0 at ahci0: 32 targets > sd0 at scsibus0 targ 0 lun 0: <ATA, Hitachi HUA72201, JP4O> SCSI3 > 0/direct fixed naa.5000cca375e4aaec > sd0: 953869MB, 512 bytes/sector, 1953525168 sectors > sd1 at scsibus0 targ 1 lun 0: <ATA, Hitachi HUA72201, JP4O> SCSI3 > 0/direct fixed naa.5000cca39adc8be4 > sd1: 953869MB, 512 bytes/sector, 1953525168 sectors > ichiic0 at pci0 dev 31 function 3 "Intel 3400 SMBus" rev 0x05: apic 8 int 18 > iic0 at ichiic0 > sdtemp0 at iic0 addr 0x18: se97 > sdtemp1 at iic0 addr 0x1a: se97 > "eeprom" at iic0 addr 0x50 not configured > "eeprom" at iic0 addr 0x52 not configured > isa0 at pcib0 > isadma0 at isa0 > com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo > com1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo > pckbc0 at isa0 port 0x60/5 > pckbd0 at pckbc0 (kbd slot) > pckbc0: using irq 1 for kbd slot > wskbd0 at pckbd0: console keyboard, using wsdisplay0 > pcppi0 at isa0 port 0x61 > spkr0 at pcppi0 > wbsio0 at isa0 port 0x2e/2: W83627DHG rev 0x25 > lm1 at wbsio0 port 0xa10/8: W83627DHG > mtrr: Pentium Pro MTRR support > uhub2 at uhub0 port 1 "Intel Rate Matching Hub" rev 2.00/0.00 addr 2 > uhidev0 at uhub2 port 2 configuration 1 interface 0 "Winbond > Electronics Corp Hermon USB hidmouse Device" rev 1.10/0.01 addr 3 > uhidev0: iclass 3/1 > ums0 at uhidev0: 3 buttons, Z dir > wsmouse0 at ums0 mux 0 > uhidev1 at uhub2 port 2 configuration 1 interface 1 "Winbond > Electronics Corp Hermon USB hidmouse Device" rev 1.10/0.01 addr 3 > uhidev1: iclass 3/1 > ukbd0 at uhidev1: 8 variable keys, 6 key codes > wskbd1 at ukbd0 mux 1 > wskbd1: connecting to wsdisplay0 > uhub3 at uhub1 port 1 "Intel Rate Matching Hub" rev 2.00/0.00 addr 2 > vscsi0 at root > scsibus1 at vscsi0: 256 targets > softraid0 at root > scsibus2 at softraid0: 256 targets > sd2 at scsibus2 targ 1 lun 0: <OPENBSD, SR RAID 1, 005> SCSI2 0/direct fixed > sd2: 953764MB, 512 bytes/sector, 1953310705 sectors > root on sd2a (e7035b2342e8b32b.a) swap on sd2b dump on sd2b
