remove some old 387 flotsam and jetsam.
Index: include/npx.h
===================================================================
RCS file: /cvs/src/sys/arch/i386/include/npx.h,v
retrieving revision 1.17
diff -u -p -r1.17 npx.h
--- include/npx.h 23 Mar 2011 16:54:35 -0000 1.17
+++ include/npx.h 5 May 2013 02:06:28 -0000
@@ -126,15 +126,7 @@ union savefpu {
struct savexmm sv_xmm;
};
-/* Cyrix EMC memory - mapped coprocessor context switch information */
-struct emcsts {
- long em_msw; /* memory mapped status register when swtched */
- long em_tar; /* memory mapped temp A register when swtched */
- long em_dl; /* memory mapped D low register when swtched */
-};
-
/* Intel prefers long real (53 bit) precision */
-#define __BDE_NPXCW__ 0x1272 /* FreeBSD */
#define __OpenBSD_NPXCW__ 0x37f
/*
@@ -150,8 +142,6 @@ struct emcsts {
* 64-bit precision
* all exceptions masked.
*/
-
-#define __INITIAL_NPXCW__ __OpenBSD_NPXCW__
void process_xmm_to_s87(const struct savexmm *, struct save87 *);
void process_s87_to_xmm(const struct save87 *, struct savexmm *);
Index: include/pcb.h
===================================================================
RCS file: /cvs/src/sys/arch/i386/include/pcb.h,v
retrieving revision 1.16
diff -u -p -r1.16 pcb.h
--- include/pcb.h 23 Mar 2011 16:54:35 -0000 1.16
+++ include/pcb.h 5 May 2013 02:06:28 -0000
@@ -63,7 +63,6 @@ struct pcb {
int pcb_ldt_len; /* number of LDT entries */
union savefpu pcb_savefpu; /* floating point state for FPU */
int pcb_cr0; /* saved image of CR0 */
- struct emcsts pcb_saveemc; /* Cyrix EMC state */
struct segment_descriptor pcb_threadsegs[2];
/* per-thread descriptors */
/*
Index: isa/npx.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/isa/npx.c,v
retrieving revision 1.57
diff -u -p -r1.57 npx.c
--- isa/npx.c 11 Jul 2011 15:40:47 -0000 1.57
+++ isa/npx.c 5 May 2013 02:06:28 -0000
@@ -770,10 +770,6 @@ npxdna_s87(struct cpu_info *ci)
* not trigger an error (e.g., fnclex). On at least one 486
* system all of the no-wait instructions are broken the same
* as frstor, so our treatment does not amplify the breakage.
- * On at least one 386/Cyrix 387 system, fnclex works correctly
- * while frstor and fnsave are broken, so our treatment breaks
- * fnclex if it is the first FPU instruction after a context
- * switch.
*/
frstor(&sfp->sv_87);
}
@@ -813,14 +809,6 @@ npxsave_cpu(struct cpu_info *ci, int sav
* Set ci->ci_fpsaving, so that any pending exception will be
* thrown away. (It will be caught again if/when the FPU
* state is restored.)
- *
- * XXX on i386 and earlier, this routine should always be
- * called at spl0; if it might called with the NPX interrupt
- * masked, it would be necessary to forcibly unmask the NPX
- * interrupt so that it could succeed.
- * XXX this is irrelevant on 486 and above (systems
- * which report FP failures via traps rather than irq13).
- * XXX punting for now..
*/
clts();
ci->ci_fpsaving = 1;
@@ -915,7 +903,7 @@ fpu_kernel_enter(void)
/* Initialize the FPU */
fninit();
- cw = __INITIAL_NPXCW__;
+ cw = __OpenBSD_NPXCW__;
fldcw(&cw);
if (i386_has_sse || i386_has_sse2) {
cw = __INITIAL_MXCSR__;
