This diff updates libdrm to the latest upstream release. Might do
with some testing, especially on radeondrm. You'll need the kernel
header changes that I just committed to be able to build this.
Index: Makefile.inc
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/Makefile.inc,v
retrieving revision 1.7
diff -u -p -r1.7 Makefile.inc
--- Makefile.inc 8 Jul 2013 09:10:05 -0000 1.7
+++ Makefile.inc 15 Nov 2013 14:00:11 -0000
@@ -1,6 +1,6 @@
# $OpenBSD: Makefile.inc,v 1.7 2013/07/08 09:10:05 jsg Exp $
-PACKAGE_VERSION= 2.4.46
+PACKAGE_VERSION= 2.4.47
NOPROFILE=
Index: xf86drm.c
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/xf86drm.c,v
retrieving revision 1.9
diff -u -p -r1.9 xf86drm.c
--- xf86drm.c 20 Jun 2013 09:55:30 -0000 1.9
+++ xf86drm.c 15 Nov 2013 13:59:50 -0000
@@ -830,6 +830,13 @@ int drmGetCap(int fd, uint64_t capabilit
return 0;
}
+int drmSetClientCap(int fd, uint64_t capability, uint64_t value)
+{
+ struct drm_set_client_cap cap = { capability, value };
+
+ return drmIoctl(fd, DRM_IOCTL_SET_CLIENT_CAP, &cap);
+}
+
/**
* Free the bus ID information.
*
Index: xf86drm.h
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/xf86drm.h,v
retrieving revision 1.7
diff -u -p -r1.7 xf86drm.h
--- xf86drm.h 25 Mar 2013 02:32:20 -0000 1.7
+++ xf86drm.h 15 Nov 2013 13:59:50 -0000
@@ -609,6 +609,8 @@ extern int drmUpdateDrawableIn
unsigned int num, void *data);
extern int drmCtlInstHandler(int fd, int irq);
extern int drmCtlUninstHandler(int fd);
+extern int drmSetClientCap(int fd, uint64_t capability,
+ uint64_t value);
/* General user-level programmer's API: authenticated client and/or X */
extern int drmMap(int fd,
Index: xf86drmMode.h
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/xf86drmMode.h,v
retrieving revision 1.5
diff -u -p -r1.5 xf86drmMode.h
--- xf86drmMode.h 8 Jul 2013 09:10:05 -0000 1.5
+++ xf86drmMode.h 15 Nov 2013 13:59:50 -0000
@@ -81,20 +81,30 @@ extern "C" {
/* Video mode flags */
/* bit compatible with the xorg definitions. */
-#define DRM_MODE_FLAG_PHSYNC (1<<0)
-#define DRM_MODE_FLAG_NHSYNC (1<<1)
-#define DRM_MODE_FLAG_PVSYNC (1<<2)
-#define DRM_MODE_FLAG_NVSYNC (1<<3)
-#define DRM_MODE_FLAG_INTERLACE (1<<4)
-#define DRM_MODE_FLAG_DBLSCAN (1<<5)
-#define DRM_MODE_FLAG_CSYNC (1<<6)
-#define DRM_MODE_FLAG_PCSYNC (1<<7)
-#define DRM_MODE_FLAG_NCSYNC (1<<8)
-#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
-#define DRM_MODE_FLAG_BCAST (1<<10)
-#define DRM_MODE_FLAG_PIXMUX (1<<11)
-#define DRM_MODE_FLAG_DBLCLK (1<<12)
-#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
+#define DRM_MODE_FLAG_PHSYNC (1<<0)
+#define DRM_MODE_FLAG_NHSYNC (1<<1)
+#define DRM_MODE_FLAG_PVSYNC (1<<2)
+#define DRM_MODE_FLAG_NVSYNC (1<<3)
+#define DRM_MODE_FLAG_INTERLACE (1<<4)
+#define DRM_MODE_FLAG_DBLSCAN (1<<5)
+#define DRM_MODE_FLAG_CSYNC (1<<6)
+#define DRM_MODE_FLAG_PCSYNC (1<<7)
+#define DRM_MODE_FLAG_NCSYNC (1<<8)
+#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
+#define DRM_MODE_FLAG_BCAST (1<<10)
+#define DRM_MODE_FLAG_PIXMUX (1<<11)
+#define DRM_MODE_FLAG_DBLCLK (1<<12)
+#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
+#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
+#define DRM_MODE_FLAG_3D_NONE (0<<14)
+#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
+#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
+#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
+#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
+#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
+#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
/* DPMS flags */
/* bit compatible with the xorg definitions. */
@@ -218,11 +228,11 @@ typedef struct _drmModeProperty {
uint32_t flags;
char name[DRM_PROP_NAME_LEN];
int count_values;
- uint64_t *values; // store the blob lengths
+ uint64_t *values; /* store the blob lengths */
int count_enums;
struct drm_mode_property_enum *enums;
int count_blobs;
- uint32_t *blob_ids; // store the blob IDs
+ uint32_t *blob_ids; /* store the blob IDs */
} drmModePropertyRes, *drmModePropertyPtr;
typedef struct _drmModeCrtc {
Index: intel/intel_bufmgr_gem.c
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/intel/intel_bufmgr_gem.c,v
retrieving revision 1.16
diff -u -p -r1.16 intel_bufmgr_gem.c
--- intel/intel_bufmgr_gem.c 8 Jul 2013 09:10:05 -0000 1.16
+++ intel/intel_bufmgr_gem.c 15 Nov 2013 13:59:49 -0000
@@ -1326,6 +1326,7 @@ int drm_intel_gem_bo_map_gtt(drm_intel_b
int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
+ drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
int ret;
/* If the CPU cache isn't coherent with the GTT, then use a
@@ -1339,7 +1340,13 @@ int drm_intel_gem_bo_map_unsynchronized(
return drm_intel_gem_bo_map_gtt(bo);
pthread_mutex_lock(&bufmgr_gem->lock);
+
ret = map_gtt(bo);
+ if (ret == 0) {
+ drm_intel_gem_bo_mark_mmaps_incoherent(bo);
+ VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
+ }
+
pthread_mutex_unlock(&bufmgr_gem->lock);
return ret;
@@ -2459,7 +2466,17 @@ drm_intel_bo_gem_create_from_prime(drm_i
if (!bo_gem)
return NULL;
- bo_gem->bo.size = size;
+ /* Determine size of bo. The fd-to-handle ioctl really should
+ * return the size, but it doesn't. If we have kernel 3.12 or
+ * later, we can lseek on the prime fd to get the size. Older
+ * kernels will just fail, in which case we fall back to the
+ * provided (estimated or guess size). */
+ ret = lseek(prime_fd, 0, SEEK_END);
+ if (ret != -1)
+ bo_gem->bo.size = ret;
+ else
+ bo_gem->bo.size = size;
+
bo_gem->bo.handle = handle;
bo_gem->bo.bufmgr = bufmgr;
Index: intel/libdrm_intel.pc.in
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/intel/libdrm_intel.pc.in,v
retrieving revision 1.1
diff -u -p -r1.1 libdrm_intel.pc.in
--- intel/libdrm_intel.pc.in 27 Jun 2009 10:02:53 -0000 1.1
+++ intel/libdrm_intel.pc.in 15 Nov 2013 13:59:49 -0000
@@ -3,8 +3,8 @@ exec_prefix=@exec_prefix@
libdir=@libdir@
includedir=@includedir@
-Name: libdrm
-Description: Userspace interface to kernel DRM services
+Name: libdrm_intel
+Description: Userspace interface to intel kernel DRM services
Version: @PACKAGE_VERSION@
Libs: -L${libdir} -ldrm -ldrm_intel
Cflags: -I${includedir} -I/usr/include/dev/pci/drm
Index: radeon/r600_pci_ids.h
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/radeon/r600_pci_ids.h,v
retrieving revision 1.4
diff -u -p -r1.4 r600_pci_ids.h
--- radeon/r600_pci_ids.h 8 Jul 2013 09:10:05 -0000 1.4
+++ radeon/r600_pci_ids.h 15 Nov 2013 13:59:49 -0000
@@ -424,3 +424,25 @@ CHIPSET(0x983C, KABINI_983C, KABINI)
CHIPSET(0x983D, KABINI_983D, KABINI)
CHIPSET(0x983E, KABINI_983E, KABINI)
CHIPSET(0x983F, KABINI_983F, KABINI)
+
+CHIPSET(0x1304, KAVERI_1304, KAVERI)
+CHIPSET(0x1305, KAVERI_1305, KAVERI)
+CHIPSET(0x1306, KAVERI_1306, KAVERI)
+CHIPSET(0x1307, KAVERI_1307, KAVERI)
+CHIPSET(0x1309, KAVERI_1309, KAVERI)
+CHIPSET(0x130A, KAVERI_130A, KAVERI)
+CHIPSET(0x130B, KAVERI_130B, KAVERI)
+CHIPSET(0x130C, KAVERI_130C, KAVERI)
+CHIPSET(0x130D, KAVERI_130D, KAVERI)
+CHIPSET(0x130E, KAVERI_130E, KAVERI)
+CHIPSET(0x130F, KAVERI_130F, KAVERI)
+CHIPSET(0x1310, KAVERI_1310, KAVERI)
+CHIPSET(0x1311, KAVERI_1311, KAVERI)
+CHIPSET(0x1312, KAVERI_1312, KAVERI)
+CHIPSET(0x1313, KAVERI_1313, KAVERI)
+CHIPSET(0x1315, KAVERI_1315, KAVERI)
+CHIPSET(0x1316, KAVERI_1316, KAVERI)
+CHIPSET(0x1317, KAVERI_1317, KAVERI)
+CHIPSET(0x131B, KAVERI_131B, KAVERI)
+CHIPSET(0x131C, KAVERI_131C, KAVERI)
+CHIPSET(0x131D, KAVERI_131D, KAVERI)
Index: radeon/radeon_cs_gem.c
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/radeon/radeon_cs_gem.c,v
retrieving revision 1.2
diff -u -p -r1.2 radeon_cs_gem.c
--- radeon/radeon_cs_gem.c 25 Mar 2013 02:32:20 -0000 1.2
+++ radeon/radeon_cs_gem.c 15 Nov 2013 13:59:49 -0000
@@ -425,6 +425,9 @@ static int cs_gem_emit(struct radeon_cs_
unsigned i;
int r;
+ while (cs->cdw & 7)
+ radeon_cs_write_dword((struct radeon_cs *)cs, 0x80000000);
+
#if CS_BOF_DUMP
cs_gem_dump_bof(cs);
#endif
Index: radeon/radeon_surface.c
===================================================================
RCS file: /home/cvs/xenocara/lib/libdrm/radeon/radeon_surface.c,v
retrieving revision 1.4
diff -u -p -r1.4 radeon_surface.c
--- radeon/radeon_surface.c 8 Jul 2013 09:10:05 -0000 1.4
+++ radeon/radeon_surface.c 15 Nov 2013 13:59:50 -0000
@@ -1382,10 +1382,16 @@ static int si_surface_sanity(struct rade
break;
case RADEON_SURF_MODE_1D:
if (surf->flags & RADEON_SURF_SBUFFER) {
- *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
+ if (surf_man->family >= CHIP_BONAIRE)
+ *stencil_tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
+ else
+ *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
}
if (surf->flags & RADEON_SURF_ZBUFFER) {
- *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
+ if (surf_man->family >= CHIP_BONAIRE)
+ *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
+ else
+ *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
} else if (surf->flags & RADEON_SURF_SCANOUT) {
*tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
} else {
@@ -1406,7 +1412,11 @@ static void si_surf_minify(struct radeon
uint32_t xalign, uint32_t yalign, uint32_t zalign,
uint32_t slice_align, unsigned offset)
{
- surflevel->npix_x = mip_minify(surf->npix_x, level);
+ if (level == 0) {
+ surflevel->npix_x = surf->npix_x;
+ } else {
+ surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
+ }
surflevel->npix_y = mip_minify(surf->npix_y, level);
surflevel->npix_z = mip_minify(surf->npix_z, level);
@@ -1428,7 +1438,7 @@ static void si_surf_minify(struct radeon
if (level == 0 && surf->last_level == 0)
/* Non-mipmap pitch padded to slice alignment */
xalign = MAX2(xalign, slice_align / surf->bpe);
- else
+ else if (surflevel->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
/* Small rows evenly distributed across slice */
xalign = MAX2(xalign, slice_align / surf->bpe / surflevel->nblk_y);
@@ -1450,7 +1460,11 @@ static void si_surf_minify_2d(struct rad
{
unsigned mtile_pr, mtile_ps;
- surflevel->npix_x = mip_minify(surf->npix_x, level);
+ if (level == 0) {
+ surflevel->npix_x = surf->npix_x;
+ } else {
+ surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
+ }
surflevel->npix_y = mip_minify(surf->npix_y, level);
surflevel->npix_z = mip_minify(surf->npix_z, level);
@@ -1643,7 +1657,10 @@ static int si_surface_init_2d(struct rad
tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
break;
case SI_TILE_MODE_DEPTH_STENCIL_2D:
- tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
+ if (surf_man->family >= CHIP_BONAIRE)
+ tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
+ else
+ tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
break;
default:
return -EINVAL;
