I've been trying to track down what's causing the cpsw device timeouts on the
beaglebone and beaglebone black. As best I can tell disabling hardware
flow control does the trick. If you're able to recreate that issue
please test this diff and report your findings. Thanks.
cvs diff: Diffing sys/arch/armv7/omap/
Index: sys/arch/armv7/omap//if_cpsw.c
===================================================================
RCS file: /cvs/src/sys/arch/armv7/omap/if_cpsw.c,v
retrieving revision 1.21
diff -u -p -u -r1.21 if_cpsw.c
--- sys/arch/armv7/omap//if_cpsw.c 26 Nov 2013 20:33:11 -0000
1.21
+++ sys/arch/armv7/omap//if_cpsw.c 14 Apr 2014 17:37:27 -0000
@@ -816,6 +816,8 @@ cpsw_init(struct ifnet *ifp)
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1);
+
+ cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
for (i = 0; i < 8; i++) {
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
Index: sys/arch/armv7/omap//if_cpswreg.h
===================================================================
RCS file: /cvs/src/sys/arch/armv7/omap/if_cpswreg.h,v
retrieving revision 1.5
diff -u -p -u -r1.5 if_cpswreg.h
--- sys/arch/armv7/omap//if_cpswreg.h 15 Nov 2013 14:31:52 -0000
1.5
+++ sys/arch/armv7/omap//if_cpswreg.h 14 Apr 2014 17:37:12 -0000
@@ -39,6 +39,7 @@
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
+#define CPSW_SS_FLOW_CONTROl (CPSW_SS_OFFSET + 0x24)
#define CPSW_PORT_OFFSET 0x0100
#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 +
((p-1) * 0x100))
