I'm looking for a few people to test some additional radeondrm fixes from the recently released Linux 3.8.13.27: https://lkml.org/lkml/2014/7/25/621
In particular on newer asics with displayport/eDP as I can only test on r100/lvds at the moment. commit 85cdd5e933c0f9fe3262067e707eed565db46378 Author: Alex Deucher <[email protected]> Date: Mon Apr 21 21:45:09 2014 -0400 drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi commit 7d5ab3009a8ca777174f6f469277b3922d56fd4b upstream. May fix display issues with non-HDMI displays. Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Kamal Mostafa <[email protected]> commit 9102ef0d290f01247918f5a519d8fa4a96eaf370 Author: Alex Deucher <[email protected]> Date: Tue May 27 16:40:51 2014 -0400 drm/radeon/atom: fix dithering on certain panels commit 642528355c694f5ed68f6bff9ff520326a249f99 upstream. We need to specify the encoder mode as LVDS for eDP when using the Crtc_Source atom table in order to properly set up the FMT hardware. bug: https://bugs.freedesktop.org/show_bug.cgi?id=73911 Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Kamal Mostafa <[email protected]> commit c9a1adc31f78a30f33c591b61171f02d13a5b1a7 Author: Alex Deucher <[email protected]> Date: Tue May 27 13:48:05 2014 -0400 drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices commit 3b6d9fd23e015b5397c438fd3cd74147d2c805b6 upstream. Only DCE5+ asics support DP 1.2. Noticed by ArtForz on IRC. Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Kamal Mostafa <[email protected]> commit 94dfc49785ea1acc1dd2c086ffd8d61ea3a5ee8f Author: Alex Deucher <[email protected]> Date: Tue May 27 13:11:36 2014 -0400 drm/radeon: fix typo in radeon_connector_is_dp12_capable() commit af5d36539dfe043f1cf0f8b7334d6bb12cd14e75 upstream. We were checking the ext clock rather than the display clock. Noticed by ArtForz on IRC. Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Kamal Mostafa <[email protected]> Index: sys/dev/pci/drm/radeon/atombios_crtc.c =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/radeon/atombios_crtc.c,v retrieving revision 1.5 diff -u -p -r1.5 atombios_crtc.c --- sys/dev/pci/drm/radeon/atombios_crtc.c 30 Mar 2014 02:17:50 -0000 1.5 +++ sys/dev/pci/drm/radeon/atombios_crtc.c 28 Jul 2014 11:25:25 -0000 @@ -840,14 +840,16 @@ static void atombios_crtc_program_pll(st args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; - switch (bpc) { - case 8: - default: - args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; - break; - case 10: - args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; - break; + if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { + switch (bpc) { + case 8: + default: + args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; + break; + case 10: + args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; + break; + } } args.v5.ucTransmitterID = encoder_id; args.v5.ucEncoderMode = encoder_mode; @@ -862,20 +864,22 @@ static void atombios_crtc_program_pll(st args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; - switch (bpc) { - case 8: - default: - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; - break; - case 10: - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; - break; - case 12: - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; - break; - case 16: - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; - break; + if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { + switch (bpc) { + case 8: + default: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; + break; + case 10: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; + break; + case 12: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; + break; + case 16: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; + break; + } } args.v6.ucTransmitterID = encoder_id; args.v6.ucEncoderMode = encoder_mode; Index: sys/dev/pci/drm/radeon/atombios_dp.c =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/radeon/atombios_dp.c,v retrieving revision 1.3 diff -u -p -r1.3 atombios_dp.c --- sys/dev/pci/drm/radeon/atombios_dp.c 10 Feb 2014 00:25:28 -0000 1.3 +++ sys/dev/pci/drm/radeon/atombios_dp.c 28 Jul 2014 11:25:25 -0000 @@ -387,6 +387,19 @@ static int dp_get_max_dp_pix_clock(int l /***** radeon specific DP functions *****/ +static int radeon_dp_get_max_link_rate(struct drm_connector *connector, + u8 dpcd[DP_DPCD_SIZE]) +{ + int max_link_rate; + + if (radeon_connector_is_dp12_capable(connector)) + max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); + else + max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); + + return max_link_rate; +} + /* First get the min lane# when low rate is used according to pixel clock * (prefer low rate), second check max lane# supported by DP panel, * if the max lane# < low rate lane# then use max lane# instead. @@ -396,7 +409,7 @@ static int radeon_dp_get_dp_lane_number( int pix_clock) { int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); - int max_link_rate = drm_dp_max_link_rate(dpcd); + int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); int max_lane_num = drm_dp_max_lane_count(dpcd); int lane_num; int max_dp_pix_clock; @@ -434,7 +447,7 @@ static int radeon_dp_get_dp_link_clock(s return 540000; } - return drm_dp_max_link_rate(dpcd); + return radeon_dp_get_max_link_rate(connector, dpcd); } static u8 radeon_dp_encoder_service(struct radeon_device *rdev, Index: sys/dev/pci/drm/radeon/atombios_encoders.c =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/radeon/atombios_encoders.c,v retrieving revision 1.7 diff -u -p -r1.7 atombios_encoders.c --- sys/dev/pci/drm/radeon/atombios_encoders.c 12 Apr 2014 06:05:53 -0000 1.7 +++ sys/dev/pci/drm/radeon/atombios_encoders.c 28 Jul 2014 11:25:25 -0000 @@ -1876,8 +1876,11 @@ atombios_set_encoder_crtc_source(struct args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; else args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); - } else + } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; + } else { args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); + } switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: Index: sys/dev/pci/drm/radeon/radeon_connectors.c =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon_connectors.c,v retrieving revision 1.3 diff -u -p -r1.3 radeon_connectors.c --- sys/dev/pci/drm/radeon/radeon_connectors.c 10 Feb 2014 00:56:17 -0000 1.3 +++ sys/dev/pci/drm/radeon/radeon_connectors.c 28 Jul 2014 11:25:25 -0000 @@ -1355,7 +1355,7 @@ bool radeon_connector_is_dp12_capable(st struct radeon_device *rdev = dev->dev_private; if (ASIC_IS_DCE5(rdev) && - (rdev->clock.dp_extclk >= 53900) && + (rdev->clock.default_dispclk >= 53900) && radeon_connector_encoder_is_hbr2(connector)) { return true; }
