I forgot a file in the diff, sorry.
diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
index 4fcc88a..8c8e0cf 100644
--- sys/arch/arm/arm/cpufunc.c
+++ sys/arch/arm/arm/cpufunc.c
@@ -1003,7 +1003,10 @@ set_cpufuncs()
(cputype & CPU_ID_CORTEX_A8_MASK) == CPU_ID_CORTEX_A8 ||
(cputype & CPU_ID_CORTEX_A9_MASK) == CPU_ID_CORTEX_A9 ||
(cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15 ||
- (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17) {
+ (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17 ||
+ (cputype & CPU_ID_CORTEX_A53_MASK) == CPU_ID_CORTEX_A53 ||
+ (cputype & CPU_ID_CORTEX_A57_MASK) == CPU_ID_CORTEX_A57 ||
+ (cputype & CPU_ID_CORTEX_A72_MASK) == CPU_ID_CORTEX_A72) {
cpufuncs = armv7_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
arm_get_cachetype_cp15v7();
diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
index 4cdbfcd..31b6419 100644
--- sys/arch/arm/include/armreg.h
+++ sys/arch/arm/include/armreg.h
@@ -245,7 +245,7 @@
#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0
#define CPU_ID_CORTEX_A72 0x410fd080
#define CPU_ID_CORTEX_A72_R1 0x411fd080
-#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0
+#define CPU_ID_CORTEX_A72_MASK 0xff0ffff0
/* ARM3-specific coprocessor 15 registers */
#define ARM3_CP15_FLUSH 1
On Wed, Mar 02, 2016 at 02:47:53PM +0100, Patrick Wildt wrote:
> Hi,
>
> apparently AArch32 of ARMv8 is backwards compatible to ARMv7,
> so we can basically run OpenBSD/armv7 on those new fancy chips.
>
> Early on set_cpufuncs() is called and makes the kernel panic if
> it can't find a setup routine for the processor it is running
> on. This diff allows set_cpufuncs() to succeed on the newer
> Cortex-A53, A57 and A72.
>
> This way, and including some other (still) local diffs, I have
> the brand new raspberry Pi 3 in multiuser: http://ix.io/oJV
>
> Patrick
>
> diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
> index 4fcc88a..8c8e0cf 100644
> --- sys/arch/arm/arm/cpufunc.c
> +++ sys/arch/arm/arm/cpufunc.c
> @@ -1003,7 +1003,10 @@ set_cpufuncs()
> (cputype & CPU_ID_CORTEX_A8_MASK) == CPU_ID_CORTEX_A8 ||
> (cputype & CPU_ID_CORTEX_A9_MASK) == CPU_ID_CORTEX_A9 ||
> (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15 ||
> - (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17) {
> + (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17 ||
> + (cputype & CPU_ID_CORTEX_A53_MASK) == CPU_ID_CORTEX_A53 ||
> + (cputype & CPU_ID_CORTEX_A57_MASK) == CPU_ID_CORTEX_A57 ||
> + (cputype & CPU_ID_CORTEX_A72_MASK) == CPU_ID_CORTEX_A72) {
> cpufuncs = armv7_cpufuncs;
> cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
> arm_get_cachetype_cp15v7();
>
