Hi,
I'd like to get some opinions on this. ARM8 has probably never ever
been used with OpenBSD, and I doubt it will ever be. I think it also
makes sense to remove more, like ARM9, ARM9E, ARM10, ARM11. All the
cruft that is not used, apart from armish, armv7 and zaurus.
In the end it will probably only make sense to support >=ARMv6, which
does not include armish and zaurus. Not sure how long those will still
be around though.
This diff removes ARM8 first, I can follow up with more diffs quickly.
Thoughts?
Patrick
diff --git sys/arch/arm/arm/cpu.c sys/arch/arm/arm/cpu.c
index bc96e79..12709b1 100644
--- sys/arch/arm/arm/cpu.c
+++ sys/arch/arm/arm/cpu.c
@@ -80,36 +80,10 @@ cpu_attach(struct device *dv)
curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK;
identify_arm_cpu(dv, curcpu());
-
-#ifdef CPU_ARM8
- if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
- int clock = arm8_clock_config(0, 0);
- char *fclk;
- aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock);
- aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : "");
- aprint_normal("%s", (clock & 2) ? " sync" : "");
- switch ((clock >> 2) & 3) {
- case 0:
- fclk = "bus clock";
- break;
- case 1:
- fclk = "ref clock";
- break;
- case 3:
- fclk = "pll";
- break;
- default:
- fclk = "illegal";
- break;
- }
- aprint_normal(" fclk source=%s\n", fclk);
- }
-#endif
}
enum cpu_class {
CPU_CLASS_NONE,
- CPU_CLASS_ARM8,
CPU_CLASS_ARM9TDMI,
CPU_CLASS_ARM9ES,
CPU_CLASS_ARM9EJS,
@@ -219,9 +193,6 @@ struct cpuidtab {
};
const struct cpuidtab cpuids[] = {
- { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810",
- generic_steppings },
-
{ CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T",
generic_steppings },
{ CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T",
@@ -358,7 +329,6 @@ struct cpu_classtab {
const struct cpu_classtab cpu_classes[] = {
{ "unknown", NULL }, /* CPU_CLASS_NONE */
- { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */
{ "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */
{ "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
{ "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
@@ -429,12 +399,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
printf("%s:", dv->dv_xname);
switch (cpu_class) {
- case CPU_CLASS_ARM8:
- if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
- printf(" IDC disabled");
- else
- printf(" IDC enabled");
- break;
case CPU_CLASS_ARM9TDMI:
case CPU_CLASS_ARM9ES:
case CPU_CLASS_ARM9EJS:
@@ -490,9 +454,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
skip_pcache:
switch (cpu_class) {
-#ifdef CPU_ARM8
- case CPU_CLASS_ARM8:
-#endif
#ifdef CPU_ARM9
case CPU_CLASS_ARM9TDMI:
#endif
diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
index f549e61..4c2c6d8 100644
--- sys/arch/arm/arm/cpufunc.c
+++ sys/arch/arm/arm/cpufunc.c
@@ -97,63 +97,6 @@ int arm_dcache_align_mask;
/* 1 == use cpu_sleep(), 0 == don't */
int cpu_do_powersave;
-#ifdef CPU_ARM8
-struct cpu_functions arm8_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- arm8_setttb, /* setttb */
- cpufunc_dfsr, /* dfsr */
- cpufunc_dfar, /* dfar */
- cpufunc_ifsr, /* ifsr */
- cpufunc_ifar, /* ifar */
-
- /* TLB functions */
-
- arm8_tlb_flushID, /* tlb_flushID */
- arm8_tlb_flushID_SE, /* tlb_flushID_SE */
- arm8_tlb_flushID, /* tlb_flushI */
- arm8_tlb_flushID_SE, /* tlb_flushI_SE */
- arm8_tlb_flushID, /* tlb_flushD */
- arm8_tlb_flushID_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- cpufunc_nullop, /* icache_sync_all */
- (void *)cpufunc_nullop, /* icache_sync_range */
-
- arm8_cache_purgeID, /* dcache_wbinv_all */
- (void *)arm8_cache_purgeID, /* dcache_wbinv_range */
-/*XXX*/ (void *)arm8_cache_purgeID, /* dcache_inv_range */
- (void *)arm8_cache_cleanID, /* dcache_wb_range */
-
- arm8_cache_purgeID, /* idcache_wbinv_all */
- (void *)arm8_cache_purgeID, /* idcache_wbinv_range */
-
- cpufunc_nullop, /* sdcache_wbinv_all */
- (void *)cpufunc_nullop, /* sdcache_wbinv_range */
- (void *)cpufunc_nullop, /* sdcache_inv_range */
- (void *)cpufunc_nullop, /* sdcache_wb_range */
-
- /* Other functions */
-
- cpufunc_nullop, /* flush_prefetchbuf */
- cpufunc_nullop, /* drain_writebuf */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
- arm8_context_switch, /* context_switch */
- arm8_setup /* cpu setup */
-};
-#endif /* CPU_ARM8 */
-
#ifdef CPU_ARM9
struct cpu_functions arm9_cpufuncs = {
/* CPU functions */
@@ -624,7 +567,7 @@ struct cpu_functions cpufuncs;
u_int cputype;
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
-#if defined(CPU_ARM8) || defined(CPU_ARM9) || \
+#if defined(CPU_ARM9) || \
defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
@@ -704,7 +647,7 @@ get_cachetype_cp15()
out:
arm_dcache_align_mask = arm_dcache_align - 1;
}
-#endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */
+#endif /* ARM7TDMI || ARM9 || XSCALE */
#if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
/* Cache information for CPUs without cache type registers. */
@@ -922,16 +865,6 @@ set_cpufuncs()
* CPU type where we want to use it by default, then we set it.
*/
-#ifdef CPU_ARM8
- if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
- (cputype & 0x0000f000) == 0x00008000) {
- cpufuncs = arm8_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
- get_cachetype_cp15();
- pmap_pte_init_arm8();
- return 0;
- }
-#endif /* CPU_ARM8 */
#ifdef CPU_ARM9
if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD ||
(cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
@@ -1197,41 +1130,6 @@ set_cpufuncs()
* CPU Setup code
*/
-#ifdef CPU_ARM8
-void
-arm8_setup()
-{
- int integer;
- int cpuctrl, cpuctrlmask;
- int clocktest;
- int setclock = 0;
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
- | CPU_CONTROL_AFLT_ENABLE;
- cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
- | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROM_ENABLE
- | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE;
-
- /* Get clock configuration */
- clocktest = arm8_clock_config(0, 0) & 0x0f;
-
- /* Clear out the cache */
- cpu_idcache_wbinv_all();
-
- /* Set the control register */
- curcpu()->ci_ctrl = cpuctrl;
- cpu_control(0xffffffff, cpuctrl);
-
- /* Set the clock/test register */
- if (setclock)
- arm8_clock_config(0x7f, clocktest);
-}
-#endif /* CPU_ARM8 */
-
#ifdef CPU_ARM9
void
arm9_setup()
diff --git sys/arch/arm/arm/pmap.c sys/arch/arm/arm/pmap.c
index dda550f..627f4d5 100644
--- sys/arch/arm/arm/pmap.c
+++ sys/arch/arm/arm/pmap.c
@@ -4439,23 +4439,6 @@ pmap_pte_init_generic(void)
pmap_zero_page_func = pmap_zero_page_generic;
}
-#if defined(CPU_ARM8)
-void
-pmap_pte_init_arm8(void)
-{
-
- /*
- * ARM8 is compatible with generic, but we need to use
- * the page tables uncached.
- */
- pmap_pte_init_generic();
-
- pte_l1_s_cache_mode_pt = 0;
- pte_l2_l_cache_mode_pt = 0;
- pte_l2_s_cache_mode_pt = 0;
-}
-#endif /* CPU_ARM8 */
-
#if defined(CPU_ARM9)
void
pmap_pte_init_arm9(void)
diff --git sys/arch/arm/conf/files.arm sys/arch/arm/conf/files.arm
index 0365078..857e7e6 100644
--- sys/arch/arm/conf/files.arm
+++ sys/arch/arm/conf/files.arm
@@ -39,7 +39,6 @@ file arch/arm/arm/bcopyinout.S
file arch/arm/arm/copystr.S
file arch/arm/arm/cpufunc.c
file arch/arm/arm/cpufunc_asm.S
-file arch/arm/arm/cpufunc_asm_arm8.S cpu_arm8
file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9
file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10
file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_arm9e |
diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
index 68fb253..f2a5854 100644
--- sys/arch/arm/include/armreg.h
+++ sys/arch/arm/include/armreg.h
@@ -176,7 +176,6 @@
#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
/* Post-ARM7 CPUs */
-#define CPU_ID_ARM810 0x41018100
#define CPU_ID_ARM920T 0x41129200
#define CPU_ID_ARM922T 0x41029220
#define CPU_ID_ARM926EJS 0x41069260
diff --git sys/arch/arm/include/cpuconf.h sys/arch/arm/include/cpuconf.h
index 4a64e12..6ed95ee 100644
--- sys/arch/arm/include/cpuconf.h
+++ sys/arch/arm/include/cpuconf.h
@@ -48,7 +48,7 @@
/*
* Determine which ARM architecture versions are configured.
*/
-#if (defined(CPU_ARM8) || defined(CPU_ARM9) || \
+#if (defined(CPU_ARM9) || \
defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
#define ARM_ARCH_4 1
@@ -91,7 +91,7 @@
* protection is not used, TEX/AP is used instead.
*/
-#if (defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \
+#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \
defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) )
#define ARM_MMU_GENERIC 1
#else
diff --git sys/arch/arm/include/cpufunc.h sys/arch/arm/include/cpufunc.h
index 9de47c4..416248a 100644
--- sys/arch/arm/include/cpufunc.h
+++ sys/arch/arm/include/cpufunc.h
@@ -213,31 +213,6 @@ u_int cpufunc_dfar (void);
u_int cpufunc_ifsr (void);
u_int cpufunc_ifar (void);
-#ifdef CPU_ARM8
-void arm8_setttb (u_int ttb);
-void arm8_tlb_flushID (void);
-void arm8_tlb_flushID_SE (u_int va);
-void arm8_cache_flushID (void);
-void arm8_cache_flushID_E (u_int entry);
-void arm8_cache_cleanID (void);
-void arm8_cache_cleanID_E (u_int entry);
-void arm8_cache_purgeID (void);
-void arm8_cache_purgeID_E (u_int entry);
-
-void arm8_cache_syncI (void);
-void arm8_cache_cleanID_rng (vaddr_t start, vsize_t end);
-void arm8_cache_cleanD_rng (vaddr_t start, vsize_t end);
-void arm8_cache_purgeID_rng (vaddr_t start, vsize_t end);
-void arm8_cache_purgeD_rng (vaddr_t start, vsize_t end);
-void arm8_cache_syncI_rng (vaddr_t start, vsize_t end);
-
-void arm8_context_switch (u_int);
-
-void arm8_setup (void);
-
-u_int arm8_clock_config (u_int, u_int);
-#endif
-
#if defined(CPU_SA1100) || defined(CPU_SA1110)
void sa11x0_drain_readbuf (void);
diff --git sys/arch/arm/include/pmap.h sys/arch/arm/include/pmap.h
index c409ad3..3851abb 100644
--- sys/arch/arm/include/pmap.h
+++ sys/arch/arm/include/pmap.h
@@ -371,9 +371,6 @@ void pmap_copy_page_generic(struct vm_page *, struct
vm_page *);
void pmap_zero_page_generic(struct vm_page *);
void pmap_pte_init_generic(void);
-#if defined(CPU_ARM8)
-void pmap_pte_init_arm8(void);
-#endif
#if defined(CPU_ARM9)
void pmap_pte_init_arm9(void);
#endif /* CPU_ARM9 */
