Hi,
based on the SA1 diff, this change also removes IXP425.
Patrick
diff --git sys/arch/arm/arm/cpu.c sys/arch/arm/arm/cpu.c
index 593bdac..5c7e385 100644
--- sys/arch/arm/arm/cpu.c
+++ sys/arch/arm/arm/cpu.c
@@ -146,13 +146,6 @@ static const char * const pxa27x_steppings[16] = {
"rev 12", "rev 13", "rev 14", "rev 15"
};
-static const char * const ixp425_steppings[16] = {
- "step 0", "rev 1", "rev 2", "rev 3",
- "rev 4", "rev 5", "rev 6", "rev 7",
- "rev 8", "rev 9", "rev 10", "rev 11",
- "rev 12", "rev 13", "rev 14", "rev 15"
-};
-
struct cpuidtab {
u_int32_t cpuid;
enum cpu_class cpu_class;
@@ -207,13 +200,6 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210",
pxa2x0_steppings },
- { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz",
- ixp425_steppings },
- { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz",
- ixp425_steppings },
- { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz",
- ixp425_steppings },
-
{ CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S",
generic_steppings },
{ CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1",
@@ -415,7 +401,7 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
#endif
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
+ defined(CPU_XSCALE_PXA2X0)
case CPU_CLASS_XSCALE:
#endif
break;
diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
index a0472f6..178bec9 100644
--- sys/arch/arm/arm/cpufunc.c
+++ sys/arch/arm/arm/cpufunc.c
@@ -66,11 +66,6 @@
#include <arm/xscale/i80321var.h>
#endif
-#ifdef CPU_XSCALE_IXP425
-#include <arm/xscale/ixp425reg.h>
-#include <arm/xscale/ixp425var.h>
-#endif
-
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
#include <arm/xscale/xscalereg.h>
#endif
@@ -328,7 +323,7 @@ struct cpu_functions armv7_cpufuncs = {
#endif /* CPU_ARMv7 */
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
+ defined(CPU_XSCALE_PXA2X0)
struct cpu_functions xscale_cpufuncs = {
/* CPU functions */
@@ -384,7 +379,7 @@ struct cpu_functions xscale_cpufuncs = {
xscale_setup /* cpu setup */
};
#endif
-/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 ||
CPU_XSCALE_IXP425 */
+/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 */
/*
* Global constants also used by locore.s
@@ -396,7 +391,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in
locore.s */
#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
+ defined(CPU_XSCALE_PXA2X0)
static void get_cachetype_cp15 (void);
/* Additional cache information local to this file. Log2 of some of the
@@ -824,23 +819,6 @@ set_cpufuncs()
return 0;
}
#endif /* CPU_XSCALE_PXA2X0 */
-#ifdef CPU_XSCALE_IXP425
- if (cputype == CPU_ID_IXP425_533 || cputype == CPU_ID_IXP425_400 ||
- cputype == CPU_ID_IXP425_266) {
- ixp425_icu_init();
-
- cpufuncs = xscale_cpufuncs;
-#if defined(PERFCTRS)
- xscale_pmu_init();
-#endif
-
- cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
- get_cachetype_cp15();
- pmap_pte_init_xscale();
-
- return 0;
- }
-#endif /* CPU_XSCALE_IXP425 */
/*
* Bzzzz. And the answer was ...
*/
@@ -967,7 +945,7 @@ armv7_setup()
#endif /* CPU_ARMv7 */
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
+ defined(CPU_XSCALE_PXA2X0)
void
xscale_setup()
{
@@ -1018,4 +996,4 @@ xscale_setup()
__asm volatile("mcr p15, 0, %0, c1, c0, 1"
: : "r" (auxctl));
}
-#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 ||
CPU_XSCALE_IXP425 */
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 */
diff --git sys/arch/arm/conf/files.arm sys/arch/arm/conf/files.arm
index fd9d508..fc37ca1 100644
--- sys/arch/arm/conf/files.arm
+++ sys/arch/arm/conf/files.arm
@@ -43,14 +43,12 @@ file arch/arm/arm/cpufunc_asm_arm10.S
cpu_arm9e | cpu_arm10
file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9e | cpu_arm10 |
cpu_xscale_80200 |
cpu_xscale_80321 |
- cpu_xscale_ixp425 |
cpu_xscale_pxa2x0
file arch/arm/arm/cpufunc_asm_armv5.S cpu_arm10
file arch/arm/arm/cpufunc_asm_armv5_ec.S cpu_arm9e | cpu_arm10
file arch/arm/arm/cpufunc_asm_armv7.S cpu_armv7
file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80200 |
cpu_xscale_80321 |
- cpu_xscale_ixp425 |
cpu_xscale_pxa2x0
file arch/arm/arm/process_machdep.c
file arch/arm/arm/sig_machdep.c
diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
index 9c10aaa..363e117 100644
--- sys/arch/arm/include/armreg.h
+++ sys/arch/arm/include/armreg.h
@@ -201,9 +201,6 @@
#define CPU_ID_80321_600 0x69052430
#define CPU_ID_80321_400_B0 0x69052c20
#define CPU_ID_80321_600_B0 0x69052c30
-#define CPU_ID_IXP425_533 0x690541c0
-#define CPU_ID_IXP425_400 0x690541d0
-#define CPU_ID_IXP425_266 0x690541f0
#define CPU_ID_CORTEX_A5 0x410fc050
#define CPU_ID_CORTEX_A5_MASK 0xff0ffff0
#define CPU_ID_CORTEX_A7 0x410fc070
diff --git sys/arch/arm/include/cpuconf.h sys/arch/arm/include/cpuconf.h
index 2ce691c..f13d03e 100644
--- sys/arch/arm/include/cpuconf.h
+++ sys/arch/arm/include/cpuconf.h
@@ -50,7 +50,7 @@
*/
#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
+ defined(CPU_XSCALE_PXA2X0))
#define ARM_ARCH_5 1
#else
#define ARM_ARCH_5 0
@@ -88,7 +88,7 @@
#endif
#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
+ defined(CPU_XSCALE_PXA2X0))
#define ARM_MMU_XSCALE 1
#else
#define ARM_MMU_XSCALE 0
diff --git sys/arch/arm/include/cpufunc.h sys/arch/arm/include/cpufunc.h
index 5ee569b..3161ee6 100644
--- sys/arch/arm/include/cpufunc.h
+++ sys/arch/arm/include/cpufunc.h
@@ -316,7 +316,7 @@ extern unsigned armv7_dcache_index_inc;
#if defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
+ defined(CPU_XSCALE_PXA2X0)
void armv4_tlb_flushID (void);
void armv4_tlb_flushI (void);
@@ -327,8 +327,7 @@ void armv4_drain_writebuf (void);
#endif
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- (ARM_MMU_XSCALE == 1)
+ defined(CPU_XSCALE_PXA2X0) || (ARM_MMU_XSCALE == 1)
void xscale_cpwait (void);
void xscale_cpu_sleep (int mode);
@@ -366,7 +365,7 @@ void xscale_cache_flushD_rng (vaddr_t start, vsize_t
end);
void xscale_context_switch (u_int);
void xscale_setup (void);
-#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 ||
CPU_XSCALE_IXP425 */
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 */
#define tlb_flush cpu_tlb_flushID
#define setttb cpu_setttb
--
2.7.0
