Hi,
I would like to get rid of even more unused CPUs, so we end up with only
armish, zaurus (armv5) and armv7. This diff removes ARM9E, but I also
have diffs prepared to get rid of ARM10 and ARM11.
ok?
Patrick
diff --git sys/arch/arm/arm/cpu.c sys/arch/arm/arm/cpu.c
index a3fe271..6fa6bc3 100644
--- sys/arch/arm/arm/cpu.c
+++ sys/arch/arm/arm/cpu.c
@@ -84,8 +84,6 @@ cpu_attach(struct device *dv)
enum cpu_class {
CPU_CLASS_NONE,
- CPU_CLASS_ARM9ES,
- CPU_CLASS_ARM9EJS,
CPU_CLASS_ARM10E,
CPU_CLASS_XSCALE,
CPU_CLASS_ARM11J,
@@ -147,15 +145,6 @@ struct cpuidtab {
};
const struct cpuidtab cpuids[] = {
- { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S",
- generic_steppings },
- { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S",
- generic_steppings },
- { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S",
- generic_steppings },
- { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S",
- generic_steppings },
-
{ CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E",
generic_steppings },
{ CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S",
@@ -255,8 +244,6 @@ struct cpu_classtab {
const struct cpu_classtab cpu_classes[] = {
{ "unknown", NULL }, /* CPU_CLASS_NONE */
- { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
- { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
{ "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
{ "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
{ "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
@@ -323,8 +310,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
printf("%s:", dv->dv_xname);
switch (cpu_class) {
- case CPU_CLASS_ARM9ES:
- case CPU_CLASS_ARM9EJS:
case CPU_CLASS_ARM10E:
case CPU_CLASS_XSCALE:
case CPU_CLASS_ARM11J:
@@ -376,10 +361,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
skip_pcache:
switch (cpu_class) {
-#ifdef CPU_ARM9E
- case CPU_CLASS_ARM9ES:
- case CPU_CLASS_ARM9EJS:
-#endif
#ifdef CPU_ARM10
case CPU_CLASS_ARM10E:
#endif
diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
index b301e13..435be3a 100644
--- sys/arch/arm/arm/cpufunc.c
+++ sys/arch/arm/arm/cpufunc.c
@@ -87,7 +87,7 @@ int arm_dcache_align_mask;
/* 1 == use cpu_sleep(), 0 == don't */
int cpu_do_powersave;
-#if defined(CPU_ARM9E) || defined(CPU_ARM10)
+#if defined(CPU_ARM10)
struct cpu_functions armv5_ec_cpufuncs = {
/* CPU functions */
@@ -143,7 +143,7 @@ struct cpu_functions armv5_ec_cpufuncs = {
arm10_context_switch, /* context_switch */
arm9e_setup /* cpu setup */
};
-#endif /* CPU_ARM9E || CPU_ARM10 */
+#endif /* CPU_ARM10 */
#ifdef CPU_ARM10
@@ -383,7 +383,7 @@ struct cpu_functions cpufuncs;
u_int cputype;
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
-#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
+#if defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0)
static void get_cachetype_cp15 (void);
@@ -461,7 +461,7 @@ get_cachetype_cp15()
out:
arm_dcache_align_mask = arm_dcache_align - 1;
}
-#endif /* ARM7TDMI || ARM9 || XSCALE */
+#endif /* ARM7TDMI || XSCALE */
#ifdef CPU_ARMv7
void arm_get_cachetype_cp15v7 (void);
@@ -627,16 +627,14 @@ set_cpufuncs()
* CPU type where we want to use it by default, then we set it.
*/
-#if defined(CPU_ARM9E) || defined(CPU_ARM10)
- if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM1026EJS) {
+#ifdef CPU_ARM10
+ if (cputype == CPU_ID_ARM1026EJS) {
cpufuncs = armv5_ec_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
pmap_pte_init_generic();
return 0;
}
-#endif /* CPU_ARM9E || CPU_ARM10 */
-#ifdef CPU_ARM10
if (/* cputype == CPU_ID_ARM1020T || */
cputype == CPU_ID_ARM1020E) {
/*
@@ -764,7 +762,7 @@ set_cpufuncs()
* CPU Setup code
*/
-#if defined(CPU_ARM9E) || defined(CPU_ARM10)
+#if defined(CPU_ARM10)
void
arm9e_setup()
{
@@ -797,9 +795,7 @@ arm9e_setup()
/* And again. */
cpu_idcache_wbinv_all();
}
-#endif /* CPU_ARM9E || CPU_ARM10 */
-#if defined(CPU_ARM10)
void
arm10_setup()
{
diff --git sys/arch/arm/conf/files.arm sys/arch/arm/conf/files.arm
index 5258a09..f021384 100644
--- sys/arch/arm/conf/files.arm
+++ sys/arch/arm/conf/files.arm
@@ -39,12 +39,12 @@ file arch/arm/arm/bcopyinout.S
file arch/arm/arm/copystr.S
file arch/arm/arm/cpufunc.c
file arch/arm/arm/cpufunc_asm.S
-file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10
-file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9e | cpu_arm10 |
+file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm10
+file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm10 |
cpu_xscale_80321 |
cpu_xscale_pxa2x0
file arch/arm/arm/cpufunc_asm_armv5.S cpu_arm10
-file arch/arm/arm/cpufunc_asm_armv5_ec.S cpu_arm9e | cpu_arm10
+file arch/arm/arm/cpufunc_asm_armv5_ec.S cpu_arm10
file arch/arm/arm/cpufunc_asm_armv7.S cpu_armv7
file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80321 |
cpu_xscale_pxa2x0
diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
index a6ae5c5..9703932 100644
--- sys/arch/arm/include/armreg.h
+++ sys/arch/arm/include/armreg.h
@@ -176,10 +176,6 @@
#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
/* Post-ARM7 CPUs */
-#define CPU_ID_ARM926EJS 0x41069260
-#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
-#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
-#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
#define CPU_ID_ARM1022ES 0x4105a220
#define CPU_ID_ARM1026EJS 0x4106a260
diff --git sys/arch/arm/include/cpuconf.h sys/arch/arm/include/cpuconf.h
index fa6f663..34b40f8 100644
--- sys/arch/arm/include/cpuconf.h
+++ sys/arch/arm/include/cpuconf.h
@@ -48,7 +48,7 @@
/*
* Determine which ARM architecture versions are configured.
*/
-#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+#if (defined(CPU_ARM10) || \
defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0))
#define ARM_ARCH_5 1
#else
@@ -79,7 +79,7 @@
* protection is not used, TEX/AP is used instead.
*/
-#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+#if (defined(CPU_ARM10) || \
defined(CPU_ARM11) || defined(CPU_ARMv7) )
#define ARM_MMU_GENERIC 1
#else
diff --git sys/arch/arm/include/cpufunc.h sys/arch/arm/include/cpufunc.h
index 394a94a..e95a958 100644
--- sys/arch/arm/include/cpufunc.h
+++ sys/arch/arm/include/cpufunc.h
@@ -213,7 +213,7 @@ u_int cpufunc_dfar (void);
u_int cpufunc_ifsr (void);
u_int cpufunc_ifar (void);
-#if defined(CPU_ARM9E) || defined(CPU_ARM10)
+#if defined(CPU_ARM10)
void arm10_tlb_flushID_SE (u_int);
void arm10_tlb_flushI_SE (u_int);
@@ -221,9 +221,7 @@ void arm10_context_switch (u_int);
void arm9e_setup (void);
void arm10_setup (void);
-#endif
-#if defined(CPU_ARM9E) || defined (CPU_ARM10)
void armv5_ec_setttb (u_int);
void armv5_ec_icache_sync_all (void);
@@ -314,7 +312,7 @@ extern unsigned armv7_dcache_index_inc;
#endif
-#if defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+#if defined(CPU_ARM10) || \
defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0)
void armv4_tlb_flushID (void);
