On Tue, Mar 22, 2016 at 12:22:55PM +0100, Patrick Wildt wrote:
> Hi,
>
> the last one to remove would be ARM11.
I forgot to mention that this diff is based on the ARM10 diff.
>
> ok?
>
> Patrick
>
> diff --git sys/arch/arm/arm/bus_space_asm_generic.S
> sys/arch/arm/arm/bus_space_asm_generic.S
> index 66727a2..fa8c0df 100644
> --- sys/arch/arm/arm/bus_space_asm_generic.S
> +++ sys/arch/arm/arm/bus_space_asm_generic.S
> @@ -50,7 +50,7 @@ ENTRY(generic_bs_r_1)
> ldrb r0, [r1, r2]
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_r_2)
> ldrh r0, [r1, r2]
> mov pc, lr
> @@ -68,7 +68,7 @@ ENTRY(generic_bs_w_1)
> strb r3, [r1, r2]
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_w_2)
> strh r3, [r1, r2]
> mov pc, lr
> @@ -96,7 +96,7 @@ ENTRY(generic_bs_rm_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_rm_2)
> add r0, r1, r2
> mov r1, r3
> @@ -144,7 +144,7 @@ ENTRY(generic_bs_wm_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_wm_2)
> add r0, r1, r2
> mov r1, r3
> @@ -192,7 +192,7 @@ ENTRY(generic_bs_rr_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_rr_2)
> add r0, r1, r2
> mov r1, r3
> @@ -240,7 +240,7 @@ ENTRY(generic_bs_wr_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_wr_2)
> add r0, r1, r2
> mov r1, r3
> @@ -287,7 +287,7 @@ ENTRY(generic_bs_sr_1)
>
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_sr_2)
> add r0, r1, r2
> mov r1, r3
> @@ -319,7 +319,7 @@ ENTRY(generic_bs_sr_4)
> * copy region
> */
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> +#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
> ENTRY(generic_armv4_bs_c_2)
> add r0, r1, r2
> ldr r2, [sp, #0]
> diff --git sys/arch/arm/arm/cpu.c sys/arch/arm/arm/cpu.c
> index df572c1..4711123 100644
> --- sys/arch/arm/arm/cpu.c
> +++ sys/arch/arm/arm/cpu.c
> @@ -85,7 +85,6 @@ cpu_attach(struct device *dv)
> enum cpu_class {
> CPU_CLASS_NONE,
> CPU_CLASS_XSCALE,
> - CPU_CLASS_ARM11J,
> CPU_CLASS_ARMv7
> };
>
> @@ -173,11 +172,6 @@ const struct cpuidtab cpuids[] = {
> { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210",
> pxa2x0_steppings },
>
> - { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S",
> - generic_steppings },
> - { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1",
> - generic_steppings },
> -
> { CPU_ID_CORTEX_A5, CPU_CLASS_ARMv7, "ARM Cortex A5",
> generic_steppings },
> { CPU_ID_CORTEX_A7, CPU_CLASS_ARMv7, "ARM Cortex A7",
> @@ -239,7 +233,6 @@ struct cpu_classtab {
> const struct cpu_classtab cpu_classes[] = {
> { "unknown", NULL }, /* CPU_CLASS_NONE */
> { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
> - { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
> { "ARMv7", "CPU_ARMv7" } /* CPU_CLASS_ARMv7 */
>
> };
> @@ -304,7 +297,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
>
> switch (cpu_class) {
> case CPU_CLASS_XSCALE:
> - case CPU_CLASS_ARM11J:
> case CPU_CLASS_ARMv7:
> if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
> printf(" DC disabled");
> @@ -353,9 +345,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
> skip_pcache:
>
> switch (cpu_class) {
> -#ifdef CPU_ARM11
> - case CPU_CLASS_ARM11J:
> -#endif
> #ifdef CPU_ARMv7
> case CPU_CLASS_ARMv7:
> #endif
> diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
> index c981f40..622f4f8 100644
> --- sys/arch/arm/arm/cpufunc.c
> +++ sys/arch/arm/arm/cpufunc.c
> @@ -87,63 +87,6 @@ int arm_dcache_align_mask;
> /* 1 == use cpu_sleep(), 0 == don't */
> int cpu_do_powersave;
>
> -#ifdef CPU_ARM11
> -struct cpu_functions arm11_cpufuncs = {
> - /* CPU functions */
> -
> - cpufunc_id, /* id */
> - cpufunc_nullop, /* cpwait */
> -
> - /* MMU functions */
> -
> - cpufunc_control, /* control */
> - cpufunc_domains, /* Domain */
> - arm11_setttb, /* Setttb */
> - cpufunc_dfsr, /* dfsr */
> - cpufunc_dfar, /* dfar */
> - cpufunc_ifsr, /* ifsr */
> - cpufunc_ifar, /* ifar */
> -
> - /* TLB functions */
> -
> - arm11_tlb_flushID, /* tlb_flushID */
> - arm11_tlb_flushID_SE, /* tlb_flushID_SE */
> - arm11_tlb_flushI, /* tlb_flushI */
> - arm11_tlb_flushI_SE, /* tlb_flushI_SE */
> - arm11_tlb_flushD, /* tlb_flushD */
> - arm11_tlb_flushD_SE, /* tlb_flushD_SE */
> -
> - /* Cache operations */
> -
> - armv5_icache_sync_all, /* icache_sync_all */
> - armv5_icache_sync_range, /* icache_sync_range */
> -
> - armv5_dcache_wbinv_all, /* dcache_wbinv_all */
> - armv5_dcache_wbinv_range, /* dcache_wbinv_range */
> -/*XXX*/ armv5_dcache_wbinv_range, /* dcache_inv_range */
> - armv5_dcache_wb_range, /* dcache_wb_range */
> -
> - armv5_idcache_wbinv_all, /* idcache_wbinv_all */
> - armv5_idcache_wbinv_range, /* idcache_wbinv_range */
> -
> - cpufunc_nullop, /* sdcache_wbinv_all */
> - (void *)cpufunc_nullop, /* sdcache_wbinv_range */
> - (void *)cpufunc_nullop, /* sdcache_inv_range */
> - (void *)cpufunc_nullop, /* sdcache_wb_range */
> -
> - /* Other functions */
> -
> - cpufunc_nullop, /* flush_prefetchbuf */
> - arm11_drain_writebuf, /* drain_writebuf */
> -
> - arm11_cpu_sleep, /* sleep (wait for interrupt) */
> -
> - /* Soft functions */
> - arm11_context_switch, /* context_switch */
> - arm11_setup /* cpu setup */
> -};
> -#endif /* CPU_ARM11 */
> -
> #ifdef CPU_ARMv7
> struct cpu_functions armv7_cpufuncs = {
> /* CPU functions */
> @@ -267,8 +210,7 @@ struct cpu_functions cpufuncs;
> u_int cputype;
> u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
>
> -#if defined(CPU_ARM11) || \
> - defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0)
> +#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0)
> static void get_cachetype_cp15 (void);
>
> /* Additional cache information local to this file. Log2 of some of the
> @@ -511,25 +453,6 @@ set_cpufuncs()
> * CPU type where we want to use it by default, then we set it.
> */
>
> -#ifdef CPU_ARM11
> - if (cputype == CPU_ID_ARM1136JS ||
> - cputype == CPU_ID_ARM1136JSR1 || 1) {
> - cpufuncs = arm11_cpufuncs;
> - cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
> - get_cachetype_cp15();
> - arm11_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
> - arm11_dcache_sets_max =
> - (1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) -
> - arm11_dcache_sets_inc;
> - arm11_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
> - arm11_dcache_index_max = 0U - arm11_dcache_index_inc;
> - pmap_pte_init_arm11();
> -
> - /* Use powersave on this CPU. */
> - cpu_do_powersave = 1;
> - return 0;
> - }
> -#endif /* CPU_ARM11 */
> #ifdef CPU_ARMv7
> if ((cputype & CPU_ID_CORTEX_A5_MASK) == CPU_ID_CORTEX_A5 ||
> (cputype & CPU_ID_CORTEX_A7_MASK) == CPU_ID_CORTEX_A7 ||
> @@ -619,36 +542,6 @@ set_cpufuncs()
> * CPU Setup code
> */
>
> -#ifdef CPU_ARM11
> -void
> -arm11_setup()
> -{
> - int cpuctrl, cpuctrlmask;
> -
> - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
> - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
> - | CPU_CONTROL_AFLT_ENABLE /* | CPU_CONTROL_BPRD_ENABLE */;
> - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
> - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
> - | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE
> - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
> - | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
> -
> - /* Clear out the cache */
> - cpu_idcache_wbinv_all();
> -
> - /* Now really make sure they are clean. */
> - asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
> -
> - /* Set the control register */
> - curcpu()->ci_ctrl = cpuctrl;
> - cpu_control(0xffffffff, cpuctrl);
> -
> - /* And again. */
> - cpu_idcache_wbinv_all();
> -}
> -#endif /* CPU_ARM11 */
> -
> #ifdef CPU_ARMv7
> void
> armv7_setup()
> diff --git sys/arch/arm/arm/pmap.c sys/arch/arm/arm/pmap.c
> index 4aac0ed..1e56461 100644
> --- sys/arch/arm/arm/pmap.c
> +++ sys/arch/arm/arm/pmap.c
> @@ -4440,29 +4440,6 @@ pmap_pte_init_generic(void)
> }
> #endif /* ARM_MMU_GENERIC == 1 */
>
> -#if defined(CPU_ARM11)
> -void
> -pmap_pte_init_arm11(void)
> -{
> -
> - /*
> - * XXX
> - * ARM11 is compatible with generic, but we want to use
> - * write-through caching for now.
> - */
> - pmap_pte_init_generic();
> -
> - pte_l1_s_cache_mode = L1_S_B | L1_S_C;
> - pte_l2_l_cache_mode = L2_B | L2_C;
> - pte_l2_s_cache_mode = L2_B | L2_C;
> -
> - pte_l1_s_cache_mode_pt = L1_S_C;
> - pte_l2_l_cache_mode_pt = L2_C;
> - pte_l2_s_cache_mode_pt = L2_C;
> -
> -}
> -#endif /* CPU_ARM11 */
> -
> #if defined(CPU_ARMv7)
> void
> pmap_pte_init_armv7(void)
> diff --git sys/arch/arm/armv7/bus_space_asm_armv7.S
> sys/arch/arm/armv7/bus_space_asm_armv7.S
> index bcb468d..6689a8d 100644
> --- sys/arch/arm/armv7/bus_space_asm_armv7.S
> +++ sys/arch/arm/armv7/bus_space_asm_armv7.S
> @@ -51,12 +51,10 @@ ENTRY(armv7_bs_r_1)
> ldrb r0, [r1, r2]
> mov pc, lr
>
> -#if (ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
> ENTRY(armv7_bs_r_2)
> dsb sy
> ldrh r0, [r1, r2]
> mov pc, lr
> -#endif
>
> ENTRY(armv7_bs_r_4)
> dsb sy
> diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
> index d194071..980681c 100644
> --- sys/arch/arm/include/armreg.h
> +++ sys/arch/arm/include/armreg.h
> @@ -131,8 +131,6 @@
>
> /* Individual CPUs are probably best IDed by everything but the revision. */
> #define CPU_ID_CPU_MASK 0xfffffff0
> -#define CPU_ID_ARM1136JS 0x4107b360
> -#define CPU_ID_ARM1136JSR1 0x4117b360
> #define CPU_ID_PXA250 0x69052100 /* sans core revision */
> #define CPU_ID_PXA210 0x69052120
> #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
> diff --git sys/arch/arm/include/cpuconf.h sys/arch/arm/include/cpuconf.h
> index b3de9cd..d9ee6fa 100644
> --- sys/arch/arm/include/cpuconf.h
> +++ sys/arch/arm/include/cpuconf.h
> @@ -54,12 +54,6 @@
> #define ARM_ARCH_5 0
> #endif
>
> -#if defined(CPU_ARM11)
> -#define ARM_ARCH_6 1
> -#else
> -#define ARM_ARCH_6 0
> -#endif
> -
> #if defined(CPU_ARMv7)
> #define ARM_ARCH_7 1
> #else
> @@ -78,7 +72,7 @@
> * protection is not used, TEX/AP is used instead.
> */
>
> -#if (defined(CPU_ARM11) || defined(CPU_ARMv7))
> +#if defined(CPU_ARMv7)
> #define ARM_MMU_GENERIC 1
> #else
> #define ARM_MMU_GENERIC 0
> diff --git sys/arch/arm/include/cpufunc.h sys/arch/arm/include/cpufunc.h
> index 168b3fa..c42a0bd 100644
> --- sys/arch/arm/include/cpufunc.h
> +++ sys/arch/arm/include/cpufunc.h
> @@ -213,45 +213,6 @@ u_int cpufunc_dfar (void);
> u_int cpufunc_ifsr (void);
> u_int cpufunc_ifar (void);
>
> -#ifdef CPU_ARM11
> -void arm11_setttb (u_int);
> -
> -void arm11_tlb_flushID_SE (u_int);
> -void arm11_tlb_flushI_SE (u_int);
> -
> -void arm11_context_switch (u_int);
> -
> -void arm11_setup (void);
> -void arm11_tlb_flushID (void);
> -void arm11_tlb_flushI (void);
> -void arm11_tlb_flushD (void);
> -void arm11_tlb_flushD_SE (u_int va);
> -
> -void arm11_drain_writebuf (void);
> -void arm11_cpu_sleep (int mode);
> -#endif
> -
> -
> -#if defined(CPU_ARM11)
> -void armv5_setttb (u_int);
> -
> -void armv5_icache_sync_all (void);
> -void armv5_icache_sync_range (vaddr_t, vsize_t);
> -
> -void armv5_dcache_wbinv_all (void);
> -void armv5_dcache_wbinv_range (vaddr_t, vsize_t);
> -void armv5_dcache_inv_range (vaddr_t, vsize_t);
> -void armv5_dcache_wb_range (vaddr_t, vsize_t);
> -
> -void armv5_idcache_wbinv_all (void);
> -void armv5_idcache_wbinv_range (vaddr_t, vsize_t);
> -
> -extern unsigned armv5_dcache_sets_max;
> -extern unsigned armv5_dcache_sets_inc;
> -extern unsigned armv5_dcache_index_max;
> -extern unsigned armv5_dcache_index_inc;
> -#endif
> -
> #ifdef CPU_ARMv7
> void armv7_setttb (u_int);
>
> diff --git sys/arch/arm/include/pmap.h sys/arch/arm/include/pmap.h
> index 0652d15c..3a1ae23 100644
> --- sys/arch/arm/include/pmap.h
> +++ sys/arch/arm/include/pmap.h
> @@ -371,9 +371,6 @@ void pmap_copy_page_generic(struct vm_page *, struct
> vm_page *);
> void pmap_zero_page_generic(struct vm_page *);
>
> void pmap_pte_init_generic(void);
> -#if defined(CPU_ARM11)
> -void pmap_pte_init_arm11(void);
> -#endif /* CPU_ARM11 */
> #if defined(CPU_ARMv7)
> void pmap_pte_init_armv7(void);
> #endif /* CPU_ARMv7 */
>
