Implementing the cp15 mmfr register with cpuid information is mandatory
for armv7 implementations (including armv8 aarch32 which uses the same
vmsa bits).
Set cpufuncs based on this instead of an ever growing list of cortex A
midr values.
Index: arm/cpufunc.c
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.41
diff -u -p -r1.41 cpufunc.c
--- arm/cpufunc.c 4 Apr 2016 09:06:28 -0000 1.41
+++ arm/cpufunc.c 16 Jul 2016 14:35:59 -0000
@@ -461,6 +461,7 @@ armv7_dcache_wbinv_all()
int
set_cpufuncs()
{
+ uint32_t mmfr0;
cputype = cpufunc_id();
cputype &= CPU_ID_CPU_MASK;
@@ -470,29 +471,31 @@ set_cpufuncs()
*/
#ifdef CPU_ARMv7
- if ((cputype & CPU_ID_CORTEX_A5_MASK) == CPU_ID_CORTEX_A5 ||
- (cputype & CPU_ID_CORTEX_A7_MASK) == CPU_ID_CORTEX_A7 ||
- (cputype & CPU_ID_CORTEX_A8_MASK) == CPU_ID_CORTEX_A8 ||
- (cputype & CPU_ID_CORTEX_A9_MASK) == CPU_ID_CORTEX_A9 ||
- (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15 ||
- (cputype & CPU_ID_CORTEX_A17_MASK) == CPU_ID_CORTEX_A17 ||
- (cputype & CPU_ID_CORTEX_A53_MASK) == CPU_ID_CORTEX_A53 ||
- (cputype & CPU_ID_CORTEX_A57_MASK) == CPU_ID_CORTEX_A57 ||
- (cputype & CPU_ID_CORTEX_A72_MASK) == CPU_ID_CORTEX_A72) {
- cpufuncs = armv7_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
- arm_get_cachetype_cp15v7();
- armv7_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
- armv7_dcache_sets_max =
- (1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) -
- armv7_dcache_sets_inc;
- armv7_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
- armv7_dcache_index_max = 0U - armv7_dcache_index_inc;
- pmap_pte_init_armv7();
+ if ((cputype & CPU_ID_ARCH_MASK) == CPU_ID_ARCH_CPUID) {
- /* Use powersave on this CPU. */
- cpu_do_powersave = 1;
- return 0;
+ __asm volatile("mrc p15, 0, %0, c0, c1, 4"
+ : "=r" (mmfr0));
+
+ switch (mmfr0 & ID_MMFR0_VMSA_MASK) {
+ case VMSA_V7:
+ case VMSA_V7_PXN:
+ case VMSA_V7_LDTF:
+ cpufuncs = armv7_cpufuncs;
+ /* V4 or higher */
+ cpu_reset_needs_v4_MMU_disable = 1;
+ arm_get_cachetype_cp15v7();
+ armv7_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
+ armv7_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
+ arm_dcache_l2_nsets)) - armv7_dcache_sets_inc;
+ armv7_dcache_index_inc = 1U << (32 -
+ arm_dcache_l2_assoc);
+ armv7_dcache_index_max = 0U - armv7_dcache_index_inc;
+ pmap_pte_init_armv7();
+
+ /* Use powersave on this CPU. */
+ cpu_do_powersave = 1;
+ return 0;
+ }
}
#endif /* CPU_ARMv7 */
#ifdef CPU_XSCALE_80321
Index: include/armreg.h
===================================================================
RCS file: /cvs/src/sys/arch/arm/include/armreg.h,v
retrieving revision 1.30
diff -u -p -r1.30 armreg.h
--- include/armreg.h 4 Apr 2016 09:06:28 -0000 1.30
+++ include/armreg.h 16 Jul 2016 14:36:00 -0000
@@ -181,6 +181,13 @@
#define CPU_ID_CORTEX_A72_R1 0x411fd080
#define CPU_ID_CORTEX_A72_MASK 0xff0ffff0
+/* CPUID on >= v7 */
+#define ID_MMFR0_VMSA_MASK 0x0000000f
+
+#define VMSA_V7 3
+#define VMSA_V7_PXN 4
+#define VMSA_V7_LDTF 5
+
/*
* Post-ARM3 CP15 registers:
*
