On Mon, Aug 01, 2016 at 10:19:17PM -0300, Daniel Bolgheroni wrote: > On Sun, Jul 31, 2016 at 08:03:58PM +0200, Mark Kettenis wrote: > > So the CPU might speculatively load TLB entries. The upshot from this > > is that we always have to perform a TLB flush if we modify a valid > > entry. So we can't rely on PV_BEEN_REFD() to decide whether we should > > flush or not. The diff below fixes thi. The diff seems to fix the > > pmap_fault_fixup() messages on a Cortex A53 system. It's very likely > > that this will fix them on Cortex A7 as well. > > Tested on Cortex-A8 and it seems ok.
My bad. This is related to the unified TLBs diff. -- db
