On Sun, Aug 07, 2016 at 01:58:06PM +0200, Mark Kettenis wrote: > The ARMv7 ARM explicitly states that all data caches in the system are > effectively PIPT. This effectively means that there is no reason to > clean or invalidate data caches except when: > > 1. We need to synchronize the instruction cache with the data cache. > > 2. We change a page to be non-cachable. > > 3. We're invoking bus_dmamap_sync() for cachable pages. > > 4. We're synching PTEs on a processor that doesn';t coherently walk > the page tables. > > This means we can remove most cases where we clean or invalidate the > data cache from pmap7.c. > > The following diff seems to work fine on Cortex-A9 and shaves another > minute and a half from the kernel build time. > > Further testing, especially on Cortex-A8, would be appreciated.
No issues notice on Cortex-A8. Kernel build remains at ~19m.
