On Sun, Aug 14, 2016 at 01:20:04PM +0200, Mark Kettenis wrote: > > Date: Sun, 14 Aug 2016 14:48:59 +1000 > > From: Jonathan Gray <[email protected]> > > > > On Sat, Aug 13, 2016 at 08:26:30PM +0200, Mark Kettenis wrote: > > > On Cortex-A7 there is a magic SMP bit in the Auxiliary Control > > > Register that "Enables coherent requests to the processor". The > > > Cortex-A7 Technical Reference Manual mentions that: > > > > > > When coherent requests are disabled: > > > > > > * loads to cacheable memory are not cached by the processor. > > > > > > So effectively, not setting the bit means that we would be running the > > > CPU with its caches disabled. We do attempt to set this bit, but the > > > code actually toggled the bit. So if the firmware had set the bit, > > > like it does on my Banana Pi, we would unset it. The result was that > > > the CPU was running at glacial speed. > > > > > > Now the Cortex-A7 TRM also has the following note: > > > > > > You must ensure this bit is set to 1 before the caches and MMU are > > > enabled, or any cache and TLB maintenance operations are > > > performed. The only time this bit is set to 0 is during a processor > > > power-down sequence. > > > > > > So we really should be setting the Auxiliary Control Register before > > > we enable the MMU and caches by setting the System Control Register. > > > The diff below fixes these issues and brings in some symbolic > > > constants for the Auxiliary Control Register bits from NetBSD. > > > > > > Tested on both Cortex-A9 and Cortex-A7. > > > > > > ok? > > > > yes ok, but the defines should really be ACTLR not AUXCTL to match > > the arm docs. > > Probably. And the CPU_CONTROL should really be SCTRL. For now I > stuck with the names that NetBSD uses. > > > Interesting that cortex a53/a57/a72 don't have a smp/coherency bit. > > I think it's basically always enabled for those. > > > Comparing to the FreeBSD code they also set/mask > > > > cortex a15: > > set (1U << 31) "snoop delayed exclusive handling" > > Looks like that's not really necessary until start doing SMP for real. > > > > > cortex a9: > > mask (1 << 7) "exclusive L1/L2 cache control" > > That setting needs to be coordinated with the L2 cache controller, > i.e. armliicc(4). But I think we currently assume that setting is > disabled. It defenitely is disabled on my cubox-i. > > > cortex a8: > > set/mask (1 << 1) Enable L2 cache > > mask (1 << 0) L1 data cache hardware alias support enabled > > Could you check what the ACTRL register is actually set to before and > after cpu_setup() is invoked on your beaglebobe? Use something like: > > __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r"(reg)); > printf("ACTLR 0x%0x\n", reg); > > to print it. We should make sure the hardware alias support is > enabled, so that bit should be zero. And hopefully the L2 cache is > already enabled as well.
It is. Before and after cpu_setup ACTLR is 0x42, so L2EN (1 << 1) and IBE (1 << 6) which is documented as Invalidates BTB enable: 0 = executes the CP15 Invalidate All and Invalidate by MVA instructions as a NOP instruction, reset value 1 = executes the CP15 Invalidate All and Invalidate by MVA instructions as specified. from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Bgbffjhh.html am335x is cortex a8 r3p2
