On Mon, Sep 19, 2016 at 11:17:09AM +0200, Mark Kettenis wrote:
> Diff below adds the relevant arm-specific code to the build.  It
> leaves out the VFP bits.  Those don't compile with our current
> toolchain (gcc/binutils) and I believe they're only necessary for the
> hard-float ABI anyway.
> 
> ok?

Sure.

AFAIK some items (in the other list) were not built as they are also
provided by libc.  What should we do about those?  Keep them or just
remove them from libc?

# These are already shipped by libc.a on arm and mips
.if ${MACHINE_CPU} != "arm" && ${MACHINE_CPU} != "mips"
SRCF+=  adddf3 \
        addsf3 \
        divdf3 \
        divsf3 \
        extendsfdf2 \
        fixdfsi \
        fixsfsi \
        floatsidf \
        floatsisf \
        muldf3 \
        mulsf3 \
        subdf3 \
        subsf3 \
        truncdfsf2
.endif

> 
> 
> Index: Makefile
> ===================================================================
> RCS file: /cvs/src/lib/libcompiler_rt/Makefile,v
> retrieving revision 1.1
> diff -u -p -r1.1 Makefile
> --- Makefile  5 Sep 2016 11:38:16 -0000       1.1
> +++ Makefile  19 Sep 2016 08:28:57 -0000
> @@ -164,6 +164,53 @@ SRCS+=   ${file}.c
>  .    endif
>  .endfor
>  
> +.if ${RTARCH} == "arm"
> +SRCS+=       aeabi_cdcmp.S \
> +     aeabi_cdcmpeq_check_nan.c \
> +     aeabi_cfcmp.S \
> +     aeabi_cfcmpeq_check_nan.c \
> +     aeabi_dcmp.S \
> +     aeabi_div0.c \
> +     aeabi_drsub.c \
> +     aeabi_fcmp.S \
> +     aeabi_frsub.c \
> +     aeabi_idivmod.S \
> +     aeabi_ldivmod.S \
> +     aeabi_memcmp.S \
> +     aeabi_memcpy.S \
> +     aeabi_memmove.S \
> +     aeabi_memset.S \
> +     aeabi_uidivmod.S \
> +     aeabi_uldivmod.S \
> +     bswapdi2.S \
> +     bswapsi2.S \
> +     switch16.S \
> +     switch32.S \
> +     switch8.S \
> +     switchu8.S \
> +     sync_fetch_and_add_4.S \
> +     sync_fetch_and_add_8.S \
> +     sync_fetch_and_and_4.S \
> +     sync_fetch_and_and_8.S \
> +     sync_fetch_and_max_4.S \
> +     sync_fetch_and_max_8.S \
> +     sync_fetch_and_min_4.S \
> +     sync_fetch_and_min_8.S \
> +     sync_fetch_and_nand_4.S \
> +     sync_fetch_and_nand_8.S \
> +     sync_fetch_and_or_4.S \
> +     sync_fetch_and_or_8.S \
> +     sync_fetch_and_sub_4.S \
> +     sync_fetch_and_sub_8.S \
> +     sync_fetch_and_umax_4.S \
> +     sync_fetch_and_umax_8.S \
> +     sync_fetch_and_umin_4.S \
> +     sync_fetch_and_umin_8.S \
> +     sync_fetch_and_xor_4.S \
> +     sync_fetch_and_xor_8.S \
> +     sync_synchronize.S
> +.endif
> +
>  .if ${RTARCH} == "ppc"
>  SRCS+=       divtc3.c \
>       fixtfdi.c \
> 

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