On Sat, Apr 01, 2017 at 06:08:23PM +1100, Jonathan Gray wrote:
> On Fri, Mar 31, 2017 at 02:03:37PM +0200, Mark Kettenis wrote:
> > On ARMv8, the translation table walk is fully coherent so there is no
> > reason to explicitly flush the cache before invalidating the TLB. The
> > barrier that is included in out TLB flushing code should be enough to
> > guarantee that the TLB walking hardware sees the updated page table
> > contents, so the explicit barriers can go as well. Diff also
> > sanitizes the code immediately around the removed bits of code to drop
> > redundant curly braces, avoid C++ style comments and removes some
> > blank lines that aren't particular useful.
> >
> > Can somebody give this a spin on hardware with a Cortex-A57 and verify
> > that this doesn't make things more unstable?
>
> I didn't encounter any problems running a make build with this change.
> It also slightly improved the build time:
>
> 291m24.74s real 257m59.41s user 16m05.09s system
> 286m32.07s real 255m44.31s user 15m22.44s system
>
I wanted to see this tested, but given this testing, ok drahn@
Dale Rahn [email protected]
