On Mon, Apr 24, 2017 at 06:48:22PM +0200, Mark Kettenis wrote:
> Even though ARM "merged" the Cortex-A12 as Cortex-A17, there are cores
> with the original Cortex-A12 MIDR out there. So it is useful to
> differentiate between them. The Rockchip RK3288 has 4 of these cores.
> The diff below adds support for these cores.
>
> As a teaser, here s a dmesg for the Asus Tinker Board. As you can
> see, it's not very useable yet (and still needs a hack to get serial
> output at the moment).
>
> OpenBSD 6.1-current (GENERIC) #51: Mon Apr 24 18:22:59 CEST 2017
>
> kette...@chopin.sibelius.xs4all.nl:/home/kettenis/src/armv7/sys/arch/armv7/compile/GENERIC
> real mem = 2147483648 (2048MB)
> avail mem = 2097512448 (2000MB)
> mainbus0 at root: Tinker-RK3288
> cpu0 at mainbus0: ARM Cortex A12 rev 1 (ARMv7 core)
> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> cpu0: 32KB(64b/l,4way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> agtimer0 at mainbus0: tick rate 24000 KHz
> com0 at mainbus0: ns16550, no working fifo
> com1 at mainbus0: ns16550, no working fifo
> com2 at mainbus0: ns16550, no working fifo
> com2: console
> com3 at mainbus0: ns16550, no working fifo
> com4 at mainbus0: ns16550, no working fifo
> ampintc0 at mainbus0 nirq 192, ncpu 4
> vscsi0 at root
> scsibus0 at vscsi0: 256 targets
> softraid0 at root
> scsibus1 at softraid0: 256 targets
> boot device: lookup 'sd0a:/bsd' failed.
> root device:
>
>
Sure, ok.
> Index: arch/arm/arm/cpu.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpu.c,v
> retrieving revision 1.36
> diff -u -p -r1.36 cpu.c
> --- arch/arm/arm/cpu.c 5 Jan 2017 16:16:17 -0000 1.36
> +++ arch/arm/arm/cpu.c 24 Apr 2017 16:36:45 -0000
> @@ -126,6 +126,8 @@ const struct cpuidtab cpuids[] = {
> generic_steppings },
> { CPU_ID_CORTEX_A9_R4, CPU_CLASS_ARMv7, "ARM Cortex A9 R4",
> generic_steppings },
> + { CPU_ID_CORTEX_A12, CPU_CLASS_ARMv7, "ARM Cortex A12",
> + generic_steppings },
> { CPU_ID_CORTEX_A15, CPU_CLASS_ARMv7, "ARM Cortex A15",
> generic_steppings },
> { CPU_ID_CORTEX_A15_R1, CPU_CLASS_ARMv7, "ARM Cortex A15 R1",
> Index: arch/arm/arm/cpufunc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpufunc.c,v
> retrieving revision 1.50
> diff -u -p -r1.50 cpufunc.c
> --- arch/arm/arm/cpufunc.c 6 Jan 2017 00:06:02 -0000 1.50
> +++ arch/arm/arm/cpufunc.c 24 Apr 2017 16:36:45 -0000
> @@ -377,6 +377,7 @@ armv7_setup()
> #endif
> /* FALLTHROUGH */
> case CPU_ID_CORTEX_A7:
> + case CPU_ID_CORTEX_A12:
> case CPU_ID_CORTEX_A15:
> case CPU_ID_CORTEX_A17:
> /* Set SMP to allow LDREX/STREX */
> Index: arch/arm/include/armreg.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/armreg.h,v
> retrieving revision 1.39
> diff -u -p -r1.39 armreg.h
> --- arch/arm/include/armreg.h 4 Jan 2017 00:40:49 -0000 1.39
> +++ arch/arm/include/armreg.h 24 Apr 2017 16:36:46 -0000
> @@ -139,6 +139,8 @@
> #define CPU_ID_CORTEX_A9_R3 0x413fc090
> #define CPU_ID_CORTEX_A9_R4 0x414fc090
> #define CPU_ID_CORTEX_A9_MASK 0xff0ffff0
> +#define CPU_ID_CORTEX_A12 0x410fc0d0
> +#define CPU_ID_CORTEX_A12_MASK 0xff0ffff0
> #define CPU_ID_CORTEX_A15 0x410fc0f0
> #define CPU_ID_CORTEX_A15_R1 0x411fc0f0
> #define CPU_ID_CORTEX_A15_R2 0x412fc0f0
>
