On Fri, Jun 16, 2017 at 02:23:36PM +0200, Mike Belopuhov wrote: > On Fri, Jun 16, 2017 at 16:31 +1000, Jonathan Matthew wrote: > > Index: arch/i386/include/cpufunc.h > > =================================================================== > > RCS file: /cvs/src/sys/arch/i386/include/cpufunc.h,v > > retrieving revision 1.25 > > diff -u -p -u -p -r1.25 cpufunc.h > > --- arch/i386/include/cpufunc.h 27 May 2017 12:21:50 -0000 1.25 > > +++ arch/i386/include/cpufunc.h 16 Jun 2017 06:07:16 -0000 > > @@ -217,6 +217,15 @@ mfence(void) > > __asm volatile("mfence" : : : "memory"); > > } > > > > +static __inline u_int64_t > > +rdtsc(void) > > +{ > > + uint32_t hi, lo; > > + > > + __asm volatile("rdtsc" : "=d" (hi), "=a" (lo)); > > + return (((uint64_t)hi << 32) | (uint64_t) lo); > > +} > > + > > static __inline void > > wrmsr(u_int msr, u_int64_t newval) > > { > > I think it's OK to get this chunk in. amd64 has got this already. >
Perhaps make it __asm volatile ("rdtsc" : "=A" (v)); like the pctr.h version? That's also what the gcc example uses for rdtsc in https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints I guess the chance of something pretending to be a 486 without TSC attaching pvbus is slim.