Hi,
so i was bored, and decided to see, if i could revive an old diff of mine,
which does separate bus_dma.h out of arm/include/bus.h, and mostly
inlines the rest in armv7/include/bus.h (credit for the idea of inlining
bus space goes to miod@).
the diff below might not be absolutely complete, i barely compile-tested
it now, but i've ran almost the same thing in the past w/o issues(ok, i had
no a4x-support/hacks in place due separate uart driver).
I would of have tested it further, but accidental 'make clean'&'make config'
and w/updated tree i now get:
sh makegap.sh 0xffffffff gapdummy.o
ld: gapdummy.o: Relocations in generic ELF (EM: 40)
ld: gapdummy.o: Relocations in generic ELF (EM: 40)
gapdummy.o: could not read symbols: File in wrong format
*** Error 1 in /usr/src/sys/arch/armv7/compile/GENERIC (Makefile:615 'gap.o')
before compilation does even begin, so i need to update my machine tomorrow,
before i can test any further, after sleep i guess.
i took the absolute bare minium i came up with my files.conf-skills(lack-of)
to solve the a4x bus space, w/rather ugly hack i must say:
diff --git a/sys/dev/ic/com.c b/sys/dev/ic/com.c
index ba3dfce322a..a9543b5938b 100644
--- a/sys/dev/ic/com.c
+++ b/sys/dev/ic/com.c
@@ -78,10 +78,10 @@
#include <ddb/db_var.h>
#endif
+#define COM_CONSOLE
#include <machine/bus.h>
#include <machine/intr.h>
-#define COM_CONSOLE
#include <dev/cons.h>
#include <dev/ic/comreg.h>
com_fdt.c(=com.c) is the only user of a4x_bs_tag.
see _bs_off()-macro in arch/armv7/include/bus.h for rest of the hack.
this diff does leave the old indirect bus space in place, to allow
ruling out bugs in the new one easier, if anyone does want to give it
a try. this diff does also remove the many duplicate bus_dma_tags around,
and renames armv7_bs_tag with mainbus_bustag and some necessary code into
arm/mainbus/mainbus.c, while removing the ugly bus_space_map_func-save-thing
from the initarm().
arm/conf/files.arm part of the diff should make it obvious, that
everything bus_space related would get concentrated into mainbus.c, while
rest would be ready for attic, that would be around -2k loc.
about ARMV7_BS_EXTENT in the diffs, well, idk if it's good for anything
but printing it in the ddb, stupid XXX i wanted to 'fix' :D
And sorry for the big diff.
-Artturi
diff --git a/sys/arch/arm/armv7/armv7_a4x_space.c
b/sys/arch/arm/armv7/armv7_a4x_space.c
index 845f7704d8d..1ee3824cc88 100644
--- a/sys/arch/arm/armv7/armv7_a4x_space.c
+++ b/sys/arch/arm/armv7/armv7_a4x_space.c
@@ -60,20 +60,19 @@ struct bus_space armv7_a4x_bs_tag = {
/* mapping/unmapping */
armv7_bs_map,
armv7_bs_unmap,
- armv7_bs_subregion,
+ mainbus_subregion,
/* allocation/deallocation */
- armv7_bs_alloc, /* not implemented */
- armv7_bs_free, /* not implemented */
+ bs_notimpl_bs_alloc, bs_notimpl_bs_free,
/* get kernel virtual address */
- armv7_bs_vaddr,
+ mainbus_vaddr,
/* mmap */
bs_notimpl_bs_mmap,
/* barrier */
- armv7_bs_barrier,
+ mainbus_barrier,
/* read (single) */
a4x_bs_r_1,
diff --git a/sys/arch/arm/armv7/armv7_space.c b/sys/arch/arm/armv7/armv7_space.c
index c7e9b686b8f..e7720722874 100644
--- a/sys/arch/arm/armv7/armv7_space.c
+++ b/sys/arch/arm/armv7/armv7_space.c
@@ -87,82 +87,9 @@ bs_protos(armv7);
bs_protos(generic);
bs_protos(bs_notimpl);
-struct bus_space armv7_bs_tag = {
- /* cookie */
- (void *) 0,
-
- /* mapping/unmapping */
- armv7_bs_map,
- armv7_bs_unmap,
- armv7_bs_subregion,
-
- /* allocation/deallocation */
- armv7_bs_alloc, /* not implemented */
- armv7_bs_free, /* not implemented */
-
- /* get kernel virtual address */
- armv7_bs_vaddr,
-
- /* mmap */
- bs_notimpl_bs_mmap,
-
- /* barrier */
- armv7_bs_barrier,
-
- /* read (single) */
- armv7_bs_r_1,
- armv7_bs_r_2,
- armv7_bs_r_4,
- bs_notimpl_bs_r_8,
-
- /* read multiple */
- armv7_bs_rm_1,
- armv7_bs_rm_2,
- armv7_bs_rm_4,
- bs_notimpl_bs_rm_8,
-
- /* read region */
- armv7_bs_rr_1,
- armv7_bs_rr_2,
- armv7_bs_rr_4,
- bs_notimpl_bs_rr_8,
-
- /* write (single) */
- armv7_bs_w_1,
- armv7_bs_w_2,
- armv7_bs_w_4,
- bs_notimpl_bs_w_8,
-
- /* write multiple */
- armv7_bs_wm_1,
- armv7_bs_wm_2,
- armv7_bs_wm_4,
- bs_notimpl_bs_wm_8,
-
- /* write region */
- armv7_bs_wr_1,
- armv7_bs_wr_2,
- armv7_bs_wr_4,
- bs_notimpl_bs_wr_8,
-
- /* set multiple */
- bs_notimpl_bs_sm_1,
- bs_notimpl_bs_sm_2,
- bs_notimpl_bs_sm_4,
- bs_notimpl_bs_sm_8,
-
- /* set region */
- armv7_bs_sr_1,
- armv7_bs_sr_2,
- armv7_bs_sr_4,
- bs_notimpl_bs_sr_8,
-
- /* copy */
- bs_notimpl_bs_c_1,
- armv7_bs_c_2,
- bs_notimpl_bs_c_4,
- bs_notimpl_bs_c_8,
-};
+extern int mainbus_attached;
+extern int bootstrap_bs_map(void *, uint64_t, bus_size_t, int,
+ bus_space_handle_t *);
int
armv7_bs_map(void *t, uint64_t bpa, bus_size_t size,
@@ -172,6 +99,9 @@ armv7_bs_map(void *t, uint64_t bpa, bus_size_t size,
vaddr_t va;
int pmap_flags = PMAP_DEVICE;
+ if (mainbus_attached == 0)
+ return bootstrap_bs_map(t, bpa, size, flags, bshp);
+
startpa = trunc_page(bpa);
endpa = round_page(bpa + size);
@@ -205,45 +135,3 @@ armv7_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t
size)
pmap_update(pmap_kernel());
uvm_km_free(kernel_map, bsh, size);
}
-
-
-int
-armv7_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
- bus_size_t size, bus_space_handle_t *nbshp)
-{
-
- *nbshp = bsh + offset;
- return (0);
-}
-
-void
-armv7_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
- bus_size_t len, int flags)
-{
- cpu_drain_writebuf();
-}
-
-void *
-armv7_bs_vaddr(void *t, bus_space_handle_t bsh)
-{
-
- return ((void *)bsh);
-}
-
-
-int
-armv7_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
- bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
- bus_addr_t *bpap, bus_space_handle_t *bshp)
-{
-
- panic("armv7_io_bs_alloc(): not implemented");
-}
-
-void
-armv7_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
-{
-
- panic("armv7_io_bs_free(): not implemented");
-}
-
diff --git a/sys/arch/arm/armv7/armv7var.h b/sys/arch/arm/armv7/armv7var.h
index 926bfaf9f83..abd3975adc4 100644
--- a/sys/arch/arm/armv7/armv7var.h
+++ b/sys/arch/arm/armv7/armv7var.h
@@ -1,4 +1,6 @@
-extern struct bus_space armv7_bs_tag;
+extern struct bus_space mainbus_bustag;
+extern struct arm32_bus_dma_tag mainbus_dma_tag;
+#ifndef BUS_SPACE_OLD
extern struct bus_space armv7_a4x_bs_tag;
-
+#endif
void armv7_intr_bootstrap(vaddr_t);
diff --git a/sys/arch/arm/conf/files.arm b/sys/arch/arm/conf/files.arm
index 9dae5a17689..55b13a813f1 100644
--- a/sys/arch/arm/conf/files.arm
+++ b/sys/arch/arm/conf/files.arm
@@ -37,8 +37,8 @@ attach cpu at mainbus
# bus_space(9)
define bus_space_generic
-file arch/arm/arm/bus_space_asm_generic.S
-file arch/arm/arm/bus_space_notimpl.S
+file arch/arm/arm/bus_space_asm_generic.S bus_space_old
+file arch/arm/arm/bus_space_notimpl.S bus_space_old
file arch/arm/arm/arm_machdep.c
file arch/arm/arm/ast.c
@@ -68,11 +68,11 @@ file arch/arm/arm/stubs.c
file arch/arm/arm/sys_machdep.c
file arch/arm/arm/vm_machdep.c
-file arch/arm/armv7/armv7_space.c cpu_armv7
-file arch/arm/armv7/armv7_a4x_space.c cpu_armv7
-file arch/arm/armv7/armv7_a4x_io.S cpu_armv7
+file arch/arm/armv7/armv7_space.c bus_space_old
+file arch/arm/armv7/armv7_a4x_space.c bus_space_old
+file arch/arm/armv7/armv7_a4x_io.S bus_space_old
file arch/arm/armv7/armv7_mutex.c cpu_armv7
-file arch/arm/armv7/bus_space_asm_armv7.S cpu_armv7
+file arch/arm/armv7/bus_space_asm_armv7.S bus_space_old
pseudo-device openprom
file arch/arm/arm/openprom.c openprom needs-flag
diff --git a/sys/arch/arm/cortex/cortex.c b/sys/arch/arm/cortex/cortex.c
index d2d6aa508b6..c9cbf0fe663 100644
--- a/sys/arch/arm/cortex/cortex.c
+++ b/sys/arch/arm/cortex/cortex.c
@@ -46,32 +46,14 @@
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
-#define _ARM32_BUS_DMA_PRIVATE
+
#include <machine/bus.h>
+
#include <arm/cpufunc.h>
#include <arm/armv7/armv7var.h>
#include <arm/cortex/cortex.h>
#include <arm/mainbus/mainbus.h>
-struct arm32_bus_dma_tag cortex_bus_dma_tag = {
- 0,
- 0,
- NULL,
- _bus_dmamap_create,
- _bus_dmamap_destroy,
- _bus_dmamap_load,
- _bus_dmamap_load_mbuf,
- _bus_dmamap_load_uio,
- _bus_dmamap_load_raw,
- _bus_dmamap_unload,
- _bus_dmamap_sync,
- _bus_dmamem_alloc,
- _bus_dmamem_free,
- _bus_dmamem_map,
- _bus_dmamem_unmap,
- _bus_dmamem_mmap,
-};
-
/* Prototypes for functions provided */
int cortexmatch(struct device *, void *, void *);
@@ -136,8 +118,8 @@ cortexsearch(struct device *parent, void *vcf, void *aux)
struct cfdata *cf = vcf;
ca.ca_name = cf->cf_driver->cd_name;
- ca.ca_iot = &armv7_bs_tag;
- ca.ca_dmat = &cortex_bus_dma_tag;
+ ca.ca_iot = &mainbus_bustag;
+ ca.ca_dmat = &mainbus_dma_tag;
ca.ca_periphbase = armv7_periphbase();
/* allow for devices to be disabled in UKC */
diff --git a/sys/arch/arm/include/bus.h b/sys/arch/arm/include/bus.h
index bb540d8acac..f799a2d2aed 100644
--- a/sys/arch/arm/include/bus.h
+++ b/sys/arch/arm/include/bus.h
@@ -62,6 +62,7 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#ifdef BUS_SPACE_OLD
#ifndef _ARM_BUS_H_
#define _ARM_BUS_H_
@@ -599,236 +600,8 @@ bs_c_2_proto(f); \
bs_c_4_proto(f); \
bs_c_8_proto(f);
-/* Bus Space DMA macros */
+#include <arm/bus_dma.h>
-/*
- * Flags used in various bus DMA methods.
- */
-#define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag)
*/
-#define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */
-#define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation
now */
-#define BUS_DMA_COHERENT 0x0004 /* hint: map memory DMA
coherent */
-#define BUS_DMA_STREAMING 0x0008 /* hint: sequential,
unidirectional */
-#define BUS_DMA_BUS1 0x0010 /* placeholders for bus
functions... */
-#define BUS_DMA_BUS2 0x0020
-#define BUS_DMA_BUS3 0x0040
-#define BUS_DMA_BUS4 0x0080
-#define BUS_DMA_READ 0x0100 /* mapping is device -> memory
only */
-#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device
only */
-#define BUS_DMA_NOCACHE 0x0400 /* hint: map non-cached memory
*/
-#define BUS_DMA_ZERO 0x0800 /* dmamem_alloc returns zeroed
mem */
-#define BUS_DMA_64BIT 0x1000 /* device handles 64bit dva */
-
-/*
- * Private flags stored in the DMA map.
- */
-#define ARM32_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on
sync */
-
-/* Forwards needed by prototypes below. */
-struct mbuf;
-struct uio;
-
-/*
- * Operations performed by bus_dmamap_sync().
- */
-#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
-#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
-#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
-#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
-
-typedef struct arm32_bus_dma_tag *bus_dma_tag_t;
-typedef struct arm32_bus_dmamap *bus_dmamap_t;
-
-#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
-
-/*
- * bus_dma_segment_t
- *
- * Describes a single contiguous DMA transaction. Values
- * are suitable for programming into DMA registers.
- */
-struct arm32_bus_dma_segment {
- /*
- * PUBLIC MEMBERS: these are used by machine-independent code.
- */
- bus_addr_t ds_addr; /* DMA address */
- bus_size_t ds_len; /* length of transfer */
- /*
- * PRIVATE MEMBERS: not for use by machine-independent code.
- */
- bus_addr_t _ds_vaddr; /* Virtual mapped address
- * Used by bus_dmamem_sync() */
- int _ds_coherent; /* Coherently mapped */
-};
-typedef struct arm32_bus_dma_segment bus_dma_segment_t;
-
-/*
- * arm32_dma_range
- *
- * This structure describes a valid DMA range.
- */
-struct arm32_dma_range {
- bus_addr_t dr_sysbase; /* system base address */
- bus_addr_t dr_busbase; /* appears here on bus */
- bus_size_t dr_len; /* length of range */
-};
-
-/*
- * bus_dma_tag_t
- *
- * A machine-dependent opaque type describing the implementation of
- * DMA for a given bus.
- */
-
-struct arm32_bus_dma_tag {
- /*
- * DMA range for this tag. If the page doesn't fall within
- * one of these ranges, an error is returned. The caller
- * may then decide what to do with the transfer. If the
- * range pointer is NULL, it is ignored.
- */
- struct arm32_dma_range *_ranges;
- int _nranges;
-
- /*
- * Opaque cookie for use by back-end.
- */
- void *_cookie;
-
- /*
- * DMA mapping methods.
- */
- int (*_dmamap_create) (bus_dma_tag_t, bus_size_t, int,
- bus_size_t, bus_size_t, int, bus_dmamap_t *);
- void (*_dmamap_destroy) (bus_dma_tag_t, bus_dmamap_t);
- int (*_dmamap_load) (bus_dma_tag_t, bus_dmamap_t, void *,
- bus_size_t, struct proc *, int);
- int (*_dmamap_load_mbuf) (bus_dma_tag_t, bus_dmamap_t,
- struct mbuf *, int);
- int (*_dmamap_load_uio) (bus_dma_tag_t, bus_dmamap_t,
- struct uio *, int);
- int (*_dmamap_load_raw) (bus_dma_tag_t, bus_dmamap_t,
- bus_dma_segment_t *, int, bus_size_t, int);
- void (*_dmamap_unload) (bus_dma_tag_t, bus_dmamap_t);
- void (*_dmamap_sync) (bus_dma_tag_t, bus_dmamap_t,
- bus_addr_t, bus_size_t, int);
-
- /*
- * DMA memory utility functions.
- */
- int (*_dmamem_alloc) (bus_dma_tag_t, bus_size_t, bus_size_t,
- bus_size_t, bus_dma_segment_t *, int, int *, int);
- void (*_dmamem_free) (bus_dma_tag_t,
- bus_dma_segment_t *, int);
- int (*_dmamem_map) (bus_dma_tag_t, bus_dma_segment_t *,
- int, size_t, caddr_t *, int);
- void (*_dmamem_unmap) (bus_dma_tag_t, caddr_t, size_t);
- paddr_t (*_dmamem_mmap) (bus_dma_tag_t, bus_dma_segment_t *,
- int, off_t, int, int);
-};
-
-#define bus_dmamap_create(t, s, n, m, b, f, p) \
- (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
-#define bus_dmamap_destroy(t, p) \
- (*(t)->_dmamap_destroy)((t), (p))
-#define bus_dmamap_load(t, m, b, s, p, f) \
- (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
-#define bus_dmamap_load_mbuf(t, m, b, f) \
- (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
-#define bus_dmamap_load_uio(t, m, u, f) \
- (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
-#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
- (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
-#define bus_dmamap_unload(t, p) \
- (*(t)->_dmamap_unload)((t), (p))
-#define bus_dmamap_sync(t, p, o, l, ops) \
- (void)((t)->_dmamap_sync ? \
- (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) : (void)0)
-
-#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
- (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
-#define bus_dmamem_free(t, sg, n) \
- (*(t)->_dmamem_free)((t), (sg), (n))
-#define bus_dmamem_map(t, sg, n, s, k, f) \
- (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
-#define bus_dmamem_unmap(t, k, s) \
- (*(t)->_dmamem_unmap)((t), (k), (s))
-#define bus_dmamem_mmap(t, sg, n, o, p, f) \
- (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
-
-/*
- * bus_dmamap_t
- *
- * Describes a DMA mapping.
- */
-struct arm32_bus_dmamap {
- /*
- * PRIVATE MEMBERS: not for use by machine-independent code.
- */
- bus_size_t _dm_size; /* largest DMA transfer mappable */
- int _dm_segcnt; /* number of segs this map can map */
- bus_size_t _dm_maxsegsz; /* largest possible segment */
- bus_size_t _dm_boundary; /* don't cross this */
- int _dm_flags; /* misc. flags */
-
- void *_dm_origbuf; /* pointer to original buffer */
- int _dm_buftype; /* type of buffer */
- struct proc *_dm_proc; /* proc that owns the mapping */
-
- void *_dm_cookie; /* cookie for bus-specific functions */
-
- /*
- * PUBLIC MEMBERS: these are used by machine-independent code.
- */
- bus_size_t dm_mapsize; /* size of the mapping */
- int dm_nsegs; /* # valid segments in mapping */
- bus_dma_segment_t dm_segs[1]; /* segments; variable length */
-};
-
-#ifdef _ARM32_BUS_DMA_PRIVATE
-
-/* _dm_buftype */
-#define ARM32_BUFTYPE_INVALID 0
-#define ARM32_BUFTYPE_LINEAR 1
-#define ARM32_BUFTYPE_MBUF 2
-#define ARM32_BUFTYPE_UIO 3
-#define ARM32_BUFTYPE_RAW 4
-
-int arm32_dma_range_intersect(struct arm32_dma_range *, int,
- paddr_t pa, psize_t size, paddr_t *pap, psize_t *sizep);
-
-int _bus_dmamap_create (bus_dma_tag_t, bus_size_t, int, bus_size_t,
- bus_size_t, int, bus_dmamap_t *);
-void _bus_dmamap_destroy (bus_dma_tag_t, bus_dmamap_t);
-int _bus_dmamap_load (bus_dma_tag_t, bus_dmamap_t, void *,
- bus_size_t, struct proc *, int);
-int _bus_dmamap_load_mbuf (bus_dma_tag_t, bus_dmamap_t,
- struct mbuf *, int);
-int _bus_dmamap_load_uio (bus_dma_tag_t, bus_dmamap_t,
- struct uio *, int);
-int _bus_dmamap_load_raw (bus_dma_tag_t, bus_dmamap_t,
- bus_dma_segment_t *, int, bus_size_t, int);
-void _bus_dmamap_unload (bus_dma_tag_t, bus_dmamap_t);
-void _bus_dmamap_sync (bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
- bus_size_t, int);
-
-int _bus_dmamem_alloc (bus_dma_tag_t tag, bus_size_t size,
- bus_size_t alignment, bus_size_t boundary,
- bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
-void _bus_dmamem_free (bus_dma_tag_t tag, bus_dma_segment_t *segs,
- int nsegs);
-int _bus_dmamem_map (bus_dma_tag_t tag, bus_dma_segment_t *segs,
- int nsegs, size_t size, caddr_t *kvap, int flags);
-void _bus_dmamem_unmap (bus_dma_tag_t tag, caddr_t kva,
- size_t size);
-paddr_t _bus_dmamem_mmap (bus_dma_tag_t tag, bus_dma_segment_t *segs,
- int nsegs, off_t off, int prot, int flags);
-
-int _bus_dmamem_alloc_range (bus_dma_tag_t tag, bus_size_t size,
- bus_size_t alignment, bus_size_t boundary,
- bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
- vaddr_t low, vaddr_t high);
-#endif /* _ARM32_BUS_DMA_PRIVATE */
/* These are OpenBSD extensions to the general NetBSD bus interface. */
void
bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
@@ -893,3 +666,4 @@ bus_space_write_raw_multi_4(bus_space_tag_t bst,
bus_space_handle_t bsh,
#endif
#endif /* _ARM_BUS_H_ */
+#endif /* BUS_SPACE_OLD */
diff --git a/sys/arch/arm/include/bus_dma.h b/sys/arch/arm/include/bus_dma.h
new file mode 100644
index 00000000000..3bfe0547f38
--- /dev/null
+++ b/sys/arch/arm/include/bus_dma.h
@@ -0,0 +1,300 @@
+/* $OpenBSD: bus.h,v 1.17 2017/05/08 00:27:45 dlg Exp $ */
+/* $NetBSD: bus.h,v 1.12 2003/10/23 15:03:24 scw Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_BUS_DMA_H_
+#define _ARM_BUS_DMA_H_
+
+/*
+ * Bus DMA implementation
+ */
+
+/*
+ * Flags used in various bus DMA methods.
+ */
+#define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag)
*/
+#define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */
+#define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation
now */
+#define BUS_DMA_COHERENT 0x0004 /* hint: map memory DMA
coherent */
+#define BUS_DMA_STREAMING 0x0008 /* hint: sequential,
unidirectional */
+#define BUS_DMA_BUS1 0x0010 /* placeholders for bus
functions... */
+#define BUS_DMA_BUS2 0x0020
+#define BUS_DMA_BUS3 0x0040
+#define BUS_DMA_BUS4 0x0080
+#define BUS_DMA_READ 0x0100 /* mapping is device -> memory
only */
+#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device
only */
+#define BUS_DMA_NOCACHE 0x0400 /* hint: map non-cached memory
*/
+#define BUS_DMA_ZERO 0x0800 /* dmamem_alloc returns zeroed
mem */
+#define BUS_DMA_64BIT 0x1000 /* device handles 64bit dva */
+
+/*
+ * Private flags stored in the DMA map.
+ */
+#define ARM32_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on
sync */
+
+/* Forwards needed by prototypes below. */
+struct mbuf;
+struct uio;
+
+/*
+ * Operations performed by bus_dmamap_sync().
+ */
+#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
+#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
+#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
+#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
+
+typedef struct arm32_bus_dma_tag *bus_dma_tag_t;
+typedef struct arm32_bus_dmamap *bus_dmamap_t;
+
+#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
+
+/*
+ * bus_dma_segment_t
+ *
+ * Describes a single contiguous DMA transaction. Values
+ * are suitable for programming into DMA registers.
+ */
+struct arm32_bus_dma_segment {
+ /*
+ * PUBLIC MEMBERS: these are used by machine-independent code.
+ */
+ bus_addr_t ds_addr; /* DMA address */
+ bus_size_t ds_len; /* length of transfer */
+ /*
+ * PRIVATE MEMBERS: not for use by machine-independent code.
+ */
+ bus_addr_t _ds_vaddr; /* Virtual mapped address
+ * Used by bus_dmamem_sync() */
+ int _ds_coherent; /* Coherently mapped */
+};
+typedef struct arm32_bus_dma_segment bus_dma_segment_t;
+
+/*
+ * arm32_dma_range
+ *
+ * This structure describes a valid DMA range.
+ */
+struct arm32_dma_range {
+ bus_addr_t dr_sysbase; /* system base address */
+ bus_addr_t dr_busbase; /* appears here on bus */
+ bus_size_t dr_len; /* length of range */
+};
+
+/*
+ * bus_dma_tag_t
+ *
+ * A machine-dependent opaque type describing the implementation of
+ * DMA for a given bus.
+ */
+
+struct arm32_bus_dma_tag {
+ /*
+ * DMA range for this tag. If the page doesn't fall within
+ * one of these ranges, an error is returned. The caller
+ * may then decide what to do with the transfer. If the
+ * range pointer is NULL, it is ignored.
+ */
+ struct arm32_dma_range *_ranges;
+ int _nranges;
+
+ /*
+ * Opaque cookie for use by back-end.
+ */
+ void *_cookie;
+
+ /*
+ * DMA mapping methods.
+ */
+ int (*_dmamap_create) (bus_dma_tag_t, bus_size_t, int,
+ bus_size_t, bus_size_t, int, bus_dmamap_t *);
+ void (*_dmamap_destroy) (bus_dma_tag_t, bus_dmamap_t);
+ int (*_dmamap_load) (bus_dma_tag_t, bus_dmamap_t, void *,
+ bus_size_t, struct proc *, int);
+ int (*_dmamap_load_mbuf) (bus_dma_tag_t, bus_dmamap_t,
+ struct mbuf *, int);
+ int (*_dmamap_load_uio) (bus_dma_tag_t, bus_dmamap_t,
+ struct uio *, int);
+ int (*_dmamap_load_raw) (bus_dma_tag_t, bus_dmamap_t,
+ bus_dma_segment_t *, int, bus_size_t, int);
+ void (*_dmamap_unload) (bus_dma_tag_t, bus_dmamap_t);
+ void (*_dmamap_sync) (bus_dma_tag_t, bus_dmamap_t,
+ bus_addr_t, bus_size_t, int);
+
+ /*
+ * DMA memory utility functions.
+ */
+ int (*_dmamem_alloc) (bus_dma_tag_t, bus_size_t, bus_size_t,
+ bus_size_t, bus_dma_segment_t *, int, int *, int);
+ void (*_dmamem_free) (bus_dma_tag_t,
+ bus_dma_segment_t *, int);
+ int (*_dmamem_map) (bus_dma_tag_t, bus_dma_segment_t *,
+ int, size_t, caddr_t *, int);
+ void (*_dmamem_unmap) (bus_dma_tag_t, caddr_t, size_t);
+ paddr_t (*_dmamem_mmap) (bus_dma_tag_t, bus_dma_segment_t *,
+ int, off_t, int, int);
+};
+
+#define bus_dmamap_create(t, s, n, m, b, f, p) \
+ (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
+#define bus_dmamap_destroy(t, p) \
+ (*(t)->_dmamap_destroy)((t), (p))
+#define bus_dmamap_load(t, m, b, s, p, f) \
+ (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
+#define bus_dmamap_load_mbuf(t, m, b, f) \
+ (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
+#define bus_dmamap_load_uio(t, m, u, f) \
+ (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
+#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
+ (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
+#define bus_dmamap_unload(t, p) \
+ (*(t)->_dmamap_unload)((t), (p))
+#define bus_dmamap_sync(t, p, o, l, ops) \
+ (void)((t)->_dmamap_sync ? \
+ (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) : (void)0)
+
+#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
+ (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
+#define bus_dmamem_free(t, sg, n) \
+ (*(t)->_dmamem_free)((t), (sg), (n))
+#define bus_dmamem_map(t, sg, n, s, k, f) \
+ (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
+#define bus_dmamem_unmap(t, k, s) \
+ (*(t)->_dmamem_unmap)((t), (k), (s))
+#define bus_dmamem_mmap(t, sg, n, o, p, f) \
+ (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
+
+/*
+ * bus_dmamap_t
+ *
+ * Describes a DMA mapping.
+ */
+struct arm32_bus_dmamap {
+ /*
+ * PRIVATE MEMBERS: not for use by machine-independent code.
+ */
+ bus_size_t _dm_size; /* largest DMA transfer mappable */
+ int _dm_segcnt; /* number of segs this map can map */
+ bus_size_t _dm_maxsegsz; /* largest possible segment */
+ bus_size_t _dm_boundary; /* don't cross this */
+ int _dm_flags; /* misc. flags */
+
+ void *_dm_origbuf; /* pointer to original buffer */
+ int _dm_buftype; /* type of buffer */
+ struct proc *_dm_proc; /* proc that owns the mapping */
+
+ void *_dm_cookie; /* cookie for bus-specific functions */
+
+ /*
+ * PUBLIC MEMBERS: these are used by machine-independent code.
+ */
+ bus_size_t dm_mapsize; /* size of the mapping */
+ int dm_nsegs; /* # valid segments in mapping */
+ bus_dma_segment_t dm_segs[1]; /* segments; variable length */
+};
+
+#ifdef _ARM32_BUS_DMA_PRIVATE
+
+/* _dm_buftype */
+#define ARM32_BUFTYPE_INVALID 0
+#define ARM32_BUFTYPE_LINEAR 1
+#define ARM32_BUFTYPE_MBUF 2
+#define ARM32_BUFTYPE_UIO 3
+#define ARM32_BUFTYPE_RAW 4
+
+int arm32_dma_range_intersect(struct arm32_dma_range *, int,
+ paddr_t pa, psize_t size, paddr_t *pap, psize_t *sizep);
+
+int _bus_dmamap_create (bus_dma_tag_t, bus_size_t, int, bus_size_t,
+ bus_size_t, int, bus_dmamap_t *);
+void _bus_dmamap_destroy (bus_dma_tag_t, bus_dmamap_t);
+int _bus_dmamap_load (bus_dma_tag_t, bus_dmamap_t, void *,
+ bus_size_t, struct proc *, int);
+int _bus_dmamap_load_mbuf (bus_dma_tag_t, bus_dmamap_t,
+ struct mbuf *, int);
+int _bus_dmamap_load_uio (bus_dma_tag_t, bus_dmamap_t,
+ struct uio *, int);
+int _bus_dmamap_load_raw (bus_dma_tag_t, bus_dmamap_t,
+ bus_dma_segment_t *, int, bus_size_t, int);
+void _bus_dmamap_unload (bus_dma_tag_t, bus_dmamap_t);
+void _bus_dmamap_sync (bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
+ bus_size_t, int);
+
+int _bus_dmamem_alloc (bus_dma_tag_t tag, bus_size_t size,
+ bus_size_t alignment, bus_size_t boundary,
+ bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
+void _bus_dmamem_free (bus_dma_tag_t tag, bus_dma_segment_t *segs,
+ int nsegs);
+int _bus_dmamem_map (bus_dma_tag_t tag, bus_dma_segment_t *segs,
+ int nsegs, size_t size, caddr_t *kvap, int flags);
+void _bus_dmamem_unmap (bus_dma_tag_t tag, caddr_t kva,
+ size_t size);
+paddr_t _bus_dmamem_mmap (bus_dma_tag_t tag, bus_dma_segment_t *segs,
+ int nsegs, off_t off, int prot, int flags);
+
+int _bus_dmamem_alloc_range (bus_dma_tag_t tag, bus_size_t size,
+ bus_size_t alignment, bus_size_t boundary,
+ bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
+ vaddr_t low, vaddr_t high);
+#endif /* _ARM32_BUS_DMA_PRIVATE */
+#endif /* _ARM_DMA_BUS_H_ */
diff --git a/sys/arch/arm/mainbus/mainbus.c b/sys/arch/arm/mainbus/mainbus.c
index 3d36366c95b..5bf6ba14ab2 100644
--- a/sys/arch/arm/mainbus/mainbus.c
+++ b/sys/arch/arm/mainbus/mainbus.c
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2016 Patrick Wildt <patr...@blueri.se>
* Copyright (c) 2017 Mark Kettenis <kette...@openbsd.org>
+ * Copyright (c) 2017 Artturi Alm
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -16,26 +17,52 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
+#define _ARM32_BUS_DMA_PRIVATE
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/malloc.h>
+#ifdef ARMV7_BS_EXTENT
+#include <sys/extent.h>
+#endif
#include <dev/ofw/openfirm.h>
#include <dev/ofw/fdt.h>
+#include <machine/bus.h>
+#include <machine/machine_reg.h>
+#include <machine/pmap.h>
+
#include <arm/mainbus/mainbus.h>
+#include <armv7/armv7/armv7_machdep.h> /* XXX */
+
+int mainbus_match(struct device *, void *, void *);
+void mainbus_attach(struct device *, struct device *, void *);
-int mainbus_match(struct device *, void *, void *);
-void mainbus_attach(struct device *, struct device *, void *);
+void mainbus_attach_node(struct device *, int, cfmatch_t);
+int mainbus_match_status(struct device *, void *, void *);
+void mainbus_attach_cpus(struct device *, cfmatch_t);
+int mainbus_match_primary(struct device *, void *, void *);
+int mainbus_match_secondary(struct device *, void *, void *);
+void mainbus_attach_framebuffer(struct device *);
-void mainbus_attach_node(struct device *, int, cfmatch_t);
-int mainbus_match_status(struct device *, void *, void *);
-void mainbus_attach_cpus(struct device *, cfmatch_t);
-int mainbus_match_primary(struct device *, void *, void *);
-int mainbus_match_secondary(struct device *, void *, void *);
-void mainbus_attach_framebuffer(struct device *);
+/*
+ * bus_space routines
+ */
+#ifdef BUS_SPACE_OLD
+int mainbus_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t,
+ bus_space_handle_t *);
+void *mainbus_vaddr(void *, bus_space_handle_t);
+#else
+int mainbus_map(bus_addr_t, bus_size_t, int, bus_space_handle_t *);
+extern int bootstrap_bs_map(void *, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *);
+void mainbus_unmap(bus_space_handle_t, bus_size_t);
+vaddr_t mapiodev(paddr_t, psize_t);
+vaddr_t bs_mapiodev(paddr_t, psize_t);
+#endif /* !BUS_SPACE_OLD */
struct mainbus_softc {
struct device sc_dev;
@@ -58,6 +85,61 @@ struct cfdriver mainbus_cd = {
NULL, "mainbus", DV_DULL
};
+#ifdef BUS_SPACE_OLD
+/* Prototypes for all the bus_space structure functions */
+bs_protos(armv7);
+/*_protos(generic);*/
+bs_protos(bs_notimpl);
+#endif /* BUS_SPACE_OLD */
+
+struct bus_space mainbus_bustag = {
+#ifndef BUS_SPACE_OLD
+ mainbus_map,
+ mainbus_unmap,
+#else
+ (void *)0,
+ /* mapping/unmapping */
+ armv7_bs_map,
+ armv7_bs_unmap,
+ mainbus_subregion,
+ /* allocation/deallocation */
+ bs_notimpl_bs_alloc, bs_notimpl_bs_free,
+ /* get kernel virtual address */
+ mainbus_vaddr,
+ /* mmap */
+ bs_notimpl_bs_mmap,
+ /* barrier */
+ mainbus_barrier,
+ /* read (single) */
+ armv7_bs_r_1, armv7_bs_r_2,
+ armv7_bs_r_4, bs_notimpl_bs_r_8,
+ /* read multiple */
+ armv7_bs_rm_1, armv7_bs_rm_2,
+ armv7_bs_rm_4, bs_notimpl_bs_rm_8,
+ /* read region */
+ armv7_bs_rr_1, armv7_bs_rr_2,
+ armv7_bs_rr_4, bs_notimpl_bs_rr_8,
+ /* write (single) */
+ armv7_bs_w_1, armv7_bs_w_2,
+ armv7_bs_w_4, bs_notimpl_bs_w_8,
+ /* write multiple */
+ armv7_bs_wm_1, armv7_bs_wm_2,
+ armv7_bs_wm_4, bs_notimpl_bs_wm_8,
+ /* write region */
+ armv7_bs_wr_1, armv7_bs_wr_2,
+ armv7_bs_wr_4, bs_notimpl_bs_wr_8,
+ /* set multiple */
+ bs_notimpl_bs_sm_1, bs_notimpl_bs_sm_2,
+ bs_notimpl_bs_sm_4, bs_notimpl_bs_sm_8,
+ /* set region */
+ armv7_bs_sr_1, armv7_bs_sr_2,
+ armv7_bs_sr_4, bs_notimpl_bs_sr_8,
+ /* copy */
+ bs_notimpl_bs_c_1, armv7_bs_c_2,
+ bs_notimpl_bs_c_4, bs_notimpl_bs_c_8,
+#endif
+};
+
struct arm32_bus_dma_tag mainbus_dma_tag = {
0,
0,
@@ -77,6 +159,25 @@ struct arm32_bus_dma_tag mainbus_dma_tag = {
_bus_dmamem_mmap,
};
+int mainbus_attached = 0;
+#ifndef BUS_SPACE_OLD
+vaddr_t last_bs_va = MACHINE_IO_AREA_VBASE;
+bus_addr_t bs_io_start = 0xffffffffU;
+bus_addr_t bs_io_end;
+#ifdef ARMV7_BS_EXTENT
+struct extent *bs_extent;
+#endif
+
+#define ADD_2_IOBS(addr,len) do { \
+ if ((addr) < bs_io_start) \
+ bs_io_start = (addr); \
+ if (((addr) + (len)) > bs_io_end) \
+ bs_io_end = (addr) + (len); \
+ } while(0)
+
+void armv7_init_devs(void);
+#endif
+
/*
* Mainbus takes care of FDT and non-FDT machines, so we
* always attach.
@@ -87,10 +188,6 @@ mainbus_match(struct device *parent, void *cfdata, void
*aux)
return (1);
}
-extern char *hw_prod;
-extern struct bus_space armv7_bs_tag;
-void platform_init_mainbus(struct device *);
-
void
mainbus_attach(struct device *parent, struct device *self, void *aux)
{
@@ -101,11 +198,21 @@ mainbus_attach(struct device *parent, struct device
*self, void *aux)
arm_intr_init_fdt();
sc->sc_node = OF_peer(0);
- sc->sc_iot = &armv7_bs_tag;
+ sc->sc_iot = &mainbus_bustag;
sc->sc_dmat = &mainbus_dma_tag;
sc->sc_acells = OF_getpropint(OF_peer(0), "#address-cells", 1);
sc->sc_scells = OF_getpropint(OF_peer(0), "#size-cells", 1);
+#ifndef BUS_SPACE_OLD
+#ifdef ARMV7_BS_EXTENT
+ bs_extent = extent_create("bus_space", bs_io_start,
+ bs_io_end, M_DEVBUF, NULL, 0, EX_NOWAIT);
+ if (bs_extent == NULL)
+ panic("unable to allocate bus_space extent");
+#endif
+#endif
+ mainbus_attached = 1;
+
len = OF_getprop(sc->sc_node, "model", model, sizeof(model));
if (len > 0) {
printf(": %s\n", model);
@@ -253,7 +360,7 @@ mainbus_match_primary(struct device *parent, void *match,
void *aux)
struct cfdata *cf = match;
uint32_t mpidr;
- __asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r " (mpidr));
+ __asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r"(mpidr));
if (fa->fa_nreg < 1 || fa->fa_reg[0].addr != (mpidr & MPIDR_AFF))
return 0;
@@ -301,3 +408,272 @@ mainbus_legacy_found(struct device *self, char *name)
config_found(self, &ma, NULL);
}
+
+#ifdef BUS_SPACE_OLD
+int
+mainbus_subregion(void *tag, bus_space_handle_t handle, bus_addr_t offset,
+ bus_size_t size, bus_space_handle_t *ret)
+{
+ *ret = handle + offset;
+ return 0;
+}
+
+void *
+mainbus_vaddr(void *tag, bus_space_handle_t handle)
+{
+ return (void *)handle;
+}
+
+void
+mainbus_barrier(void *tag, bus_space_handle_t handle, bus_size_t offset,
+ bus_size_t size, int flags)
+{
+ cpu_drain_writebuf();
+}
+#endif
+
+#ifndef BUS_SPACE_OLD
+int
+mainbus_map(bus_addr_t addr, bus_size_t size, int fl, bus_space_handle_t *ret)
+{
+ vaddr_t map;
+
+ if (fl & BUS_SPACE_MAP_CACHEABLE)
+ addr |= 1;
+
+ map = mapiodev((paddr_t)addr, size);
+ if (map == 0)
+ return ENOMEM;
+
+ *ret = (bus_space_handle_t)map;
+ return 0;
+}
+
+void
+mainbus_unmap(bus_space_handle_t handle, bus_size_t size)
+{
+ vaddr_t eva, kva, off;
+ vsize_t vsize;
+ paddr_t pa;
+#ifdef ARMV7_BS_EXTENT
+ int s, error;
+#endif
+
+ if (mainbus_attached == 0)
+ return;
+
+ /* sanity checks */
+ if (size <= 0)
+ return;
+ vsize = (vsize_t)size;
+ eva = kva + vsize;
+ if (eva < kva && eva != 0)
+ return;
+
+ /* check for bs_io mapping */
+ if (kva >= bs_io_start) {
+ if (bs_io_end == 0 || eva > bs_io_end)
+ return;
+ else if (kva >= bs_io_end)
+ /* across bs_io and non-bs_io, not supported */
+ return;
+ }
+
+ off = va & PGOFSET;
+ kva = trunc_page(kva);
+ vsize = round_page(off + vsize);
+
+ if (pmap_extract(pmap_kernel(), kva, &pa) == FALSE)
+ panic("mainbus_unmap(%#lx, %#lx)", kva, vsize);
+
+ pmap_kremove(kva, kva + size);
+ pmap_update(pmap_kernel());
+ uvm_km_free(kernel_map, kva, size);
+
+#ifdef ARMV7_BS_EXTENT
+ s = splhigh();
+ error = extent_free(bs_extent, atop(pa), atop(vsize),
+ EX_MALLOCOK | (cold ? 0 : EX_WAITSPACE));
+ splx(s);
+#ifdef DIAGNOSTIC
+ if (error != 0)
+ printf("%s(%#lx pa %#lx, %#lx): extent_free failed\n",
+ __func__, kva, pa, vsize);
+#endif
+#endif
+}
+
+/*
+ * Map a range [pa, pa+size) in the given map to a kernel address
+ * in iomap space.
+ *
+ * Note: To be flexible, I did not put a restriction on the alignment
+ * of pa. However, it is advisable to have pa page aligned since otherwise,
+ * we might have several mappings for a given chunk of the IO page XXX not.
+ */
+vaddr_t
+mapiodev(paddr_t addr, int _size)
+{
+ vaddr_t va, iova, off;
+ paddr_t pa, epa;
+ psize_t size;
+ pt_entry_t *pte;
+ u_int pm_flags;
+#ifdef ARMV7_BS_EXTENT
+ int error, s;
+#endif
+ pm_flags = addr & 1 ? PMAP_DEVICE : 0;
+ addr &= ~1;
+
+ /* sanity checks */
+ if (_size <= 0)
+ return 0;
+ size = (psize_t)_size;
+ epa = addr + size;
+ if (epa < addr && epa != 0)
+ return 0;
+
+#if 0 /* XXX related to omap/bbb failing to boot?!?! */
+ /* check for bs_io mapping */
+ if (!mainbus_attached && addr >= bs_io_start) {
+ /*
+ * XXX should this adjust bs_io_end incase
+ * addr <= bs_io_end && epa >= bs_io_end ??
+ */
+ if (bs_io_end == 0 || epa <= bs_io_end)
+ return bs_mapiodev(addr, size);
+ else if (addr <= bs_io_end)
+ /* across obio and non-obio, not supported */
+ return 0;
+ }
+#else
+ if (!mainbus_attached)
+ return bs_mapiodev(addr, size);
+#endif
+
+ pa = trunc_page(addr);
+ off = addr & PGOFSET;
+ size = round_page(epa - pa);
+
+#ifdef ARMV7_BS_EXTENT
+ s = splhigh();
+ error = extent_alloc_region(bs_extent, pa, size,
+ EX_MALLOCOK | EX_CONFLICTOK);
+ splx(s);
+ if (error != 0)
+ return 0;
+#endif
+
+ va = uvm_km_valloc(kernel_map, size);
+ if (va == 0) {
+#ifdef ARMV7_BS_EXTENT
+ extent_free(bs_extent, atop(pa), atop(size),
+ EX_MALLOCOK | EX_CONFLICTOK);
+#endif
+ return 0;
+ }
+
+ iova = va + off;
+ for (epa = pa + size; pa < epa; pa += PAGE_SIZE, va += PAGE_SIZE)
+ pmap_kenter_pa(va, pa | pm_flags, PROT_READ | PROT_WRITE);
+ pmap_update(pmap_kernel());
+
+ return iova;
+}
+
+static inline vaddr_t
+_cur_ttb(void)
+{
+ vadd_t ttb;
+ __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(ttb));
+ return ttb & ~0x3fff; /* truncate to 16K */
+}
+vaddr_t
+bs_mapiodev(paddr_t addr, psize_t size)
+{
+ vaddr_t iova, va, off;
+ paddr_t pa, epa;
+ u_int pm_flags;
+ vaddr_t pt = _cur_ttb();
+
+ pa = addr & L1S_FRAME;
+ off = addr & L1S_OFFSET;
+ size = ((off + size) + L1S_OFFSET) & L1S_FRAME;
+
+ va = last_bs_va;
+
+ iova = va + off;
+ for (epa = pa + size; pa < epa; pa += L1S_SIZE, va += L1S_SIZE)
+ pmap_map_section(pt, va, pa, PROT_READ | PROT_WRITE,
+ PTE_NOCACHE);
+ last_bs_va = va;
+
+ cpu_tlb_flushID();
+ cpu_drain_writebuf();
+
+ return iova;
+}
+
+/*
+ * Should we ADD_2_IOBS() this node?
+ */
+void
+mainbus_check_node(int node, int a_cells, int s_cells)
+{
+ int i, len, line, nreg;
+ u_int tmpreg[64]
+ u_int *cell, *reg = &tmpreg[0];
+ u_int pa, sz;
+
+#if 0
+ if (OF_getprop(node, "status", buf, sizeof(buf)) > 0 &&
+ strcmp(buf, "disabled") == 0)
+ return;
+#endif
+ if (a_cells > 2 || s_cells > 2)
+ return;
+
+ len = max(OF_getproplen(node, "reg"), 64 * sizeof(u_int));
+ line = (a_cells + s_cells) * sizeof(u_int);
+ nreg = len / line;
+ if (len > 0 && (len % line) == 0) {
+ OF_getpropintarray(node, "reg", reg, len);
+
+ for (i = 0, cell = reg; i < nreg; i++) {
+ if (a_cells == 1)
+ pa = cell[0];
+ else if (a_cells == 2)
+ pa = cell[1];
+ else
+ pa = 0;
+ cell += a_cells;
+
+ if (s_cells == 1)
+ sz = cell[0];
+ else if (s_cells == 2)
+ sz = cell[1];
+ else
+ sz = 0;
+ cell += s_cells;
+
+ if (pa && sz)
+ ADD_2_IOBS(pa, sz);
+ }
+ }
+}
+
+void
+armv7_scan_devs(void)
+{
+ int _node = OF_peer(0);
+ int a_cells = OF_getpropint(OF_peer(0), "#address-cells", 1);
+ int s_cells = OF_getpropint(OF_peer(0), "#size-cells", 1);
+ int node;
+
+ /* Scan the whole tree. */
+ for (node = OF_child(_node); node != 0; node = OF_peer(node))
+ mainbus_check_node(node, a_cells, s_cells);
+
+ printf("%s: done %#lx %#lx\n", __func__, bs_io_start, bs_io_end);
+}
+#endif
diff --git a/sys/arch/armv7/armv7/armv7.c b/sys/arch/armv7/armv7/armv7.c
index c57fb56738a..4e120a83979 100644
--- a/sys/arch/armv7/armv7/armv7.c
+++ b/sys/arch/armv7/armv7/armv7.c
@@ -21,31 +21,12 @@
#include <sys/types.h>
#include <sys/malloc.h>
-#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
+
#include <arm/armv7/armv7var.h>
#include <armv7/armv7/armv7var.h>
#include <armv7/armv7/armv7_machdep.h>
-struct arm32_bus_dma_tag armv7_bus_dma_tag = {
- 0,
- 0,
- NULL,
- _bus_dmamap_create,
- _bus_dmamap_destroy,
- _bus_dmamap_load,
- _bus_dmamap_load_mbuf,
- _bus_dmamap_load_uio,
- _bus_dmamap_load_raw,
- _bus_dmamap_unload,
- _bus_dmamap_sync,
- _bus_dmamem_alloc,
- _bus_dmamem_free,
- _bus_dmamem_map,
- _bus_dmamem_unmap,
- _bus_dmamem_mmap,
-};
-
struct armv7_dev *armv7_devs = NULL;
#define DEVNAME(sc) (sc)->sc_dv.dv_xname
@@ -115,12 +96,11 @@ armv7_attach(struct device *parent, struct device *self,
void *aux)
memset(&aa, 0, sizeof(aa));
aa.aa_dev = ad;
- aa.aa_iot = &armv7_bs_tag;
- aa.aa_dmat = &armv7_bus_dma_tag;
+ aa.aa_iot = &mainbus_bustag;
+ aa.aa_dmat = &mainbus_dma_tag;
if (config_found_sm(self, &aa, NULL, armv7_submatch) == NULL)
printf("%s: device %s unit %d not configured\n",
DEVNAME(sc), bd->name, bd->unit);
}
}
-
diff --git a/sys/arch/armv7/armv7/armv7_machdep.c
b/sys/arch/armv7/armv7/armv7_machdep.c
index aa1c549b29b..a39fc1cd29b 100644
--- a/sys/arch/armv7/armv7/armv7_machdep.c
+++ b/sys/arch/armv7/armv7/armv7_machdep.c
@@ -308,7 +308,7 @@ read_ttb(void)
* before pmap is initialized.
* ignores cacheability and does map the sections with nocache.
*/
-static vaddr_t section_free = 0xfd000000; /* XXX - huh */
+static vaddr_t section_free = MACHINE_IO_AREA_VBASE; /* XXX - huh */
int
bootstrap_bs_map(void *t, uint64_t bpa, bus_size_t size,
@@ -383,11 +383,7 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
loadaddr)
size_t size;
void *node;
extern uint32_t esym; /* &_end if no symbols are loaded */
-
- /* early bus_space_map support */
- struct bus_space tmp_bs_tag;
- int (*map_func_save)(void *, uint64_t, bus_size_t, int,
- bus_space_handle_t *);
+ extern void armv7_scan_devs(void);
if (arg0)
esym = (uint32_t)arg0;
@@ -407,19 +403,6 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
loadaddr)
panic("cpu not recognized!");
/*
- * Temporarily replace bus_space_map() functions so that
- * console devices can get mapped.
- *
- * Note that this relies upon the fact that both regular
- * and a4x bus_space tags use the same map function.
- */
- tmp_bs_tag = armv7_bs_tag;
- map_func_save = armv7_bs_tag.bs_map;
- armv7_bs_tag.bs_map = bootstrap_bs_map;
- armv7_a4x_bs_tag.bs_map = bootstrap_bs_map;
- tmp_bs_tag.bs_map = bootstrap_bs_map;
-
- /*
* Now, map the FDT area.
*
* As we don't know the size of a possible FDT, map the size of a
@@ -449,6 +432,8 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
loadaddr)
memcpy(bootduid, duid, sizeof(bootduid));
}
+ armv7_scan_devs();
+
node = fdt_find_node("/memory");
if (node == NULL || fdt_get_reg(node, 0, ®))
panic("initarm: no memory specificed");
@@ -772,12 +757,6 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
loadaddr)
vector_page_setprot(PROT_READ | PROT_EXEC);
- /*
- * Restore proper bus_space operation, now that pmap is initialized.
- */
- armv7_bs_tag.bs_map = map_func_save;
- armv7_a4x_bs_tag.bs_map = map_func_save;
-
#ifdef DDB
db_machine_init();
diff --git a/sys/arch/armv7/armv7/armv7_machdep.h
b/sys/arch/armv7/armv7/armv7_machdep.h
index ff52b0c2744..10dfe14133a 100644
--- a/sys/arch/armv7/armv7/armv7_machdep.h
+++ b/sys/arch/armv7/armv7/armv7_machdep.h
@@ -19,6 +19,7 @@
#define __PLATFORMVAR_H__
extern int stdout_node;
+extern char *hw_prod;
void platform_init(void);
void platform_powerdown(void);
diff --git a/sys/arch/armv7/conf/GENERIC b/sys/arch/armv7/conf/GENERIC
index af71a6c4835..45223028572 100644
--- a/sys/arch/armv7/conf/GENERIC
+++ b/sys/arch/armv7/conf/GENERIC
@@ -23,6 +23,7 @@ option WSDISPLAY_DEFAULTSCREENS=1
option CONF_HAVE_GPIO
option USBVERBOSE
+#option BUS_SPACE_OLD # use old indirect bus_space
config bsd swap generic
diff --git a/sys/arch/armv7/conf/RAMDISK b/sys/arch/armv7/conf/RAMDISK
index 8a11ae63cfb..f16f8b54d91 100644
--- a/sys/arch/armv7/conf/RAMDISK
+++ b/sys/arch/armv7/conf/RAMDISK
@@ -23,6 +23,7 @@ option INET6
option EXT2FS
option USBVERBOSE
+#option BUS_SPACE_OLD # use old indirect bus_space
config bsd root on rd0a swap on rd0b
diff --git a/sys/arch/armv7/dev/com_fdt.c b/sys/arch/armv7/dev/com_fdt.c
index 30b0e8683cf..1dfe5c1edfc 100644
--- a/sys/arch/armv7/dev/com_fdt.c
+++ b/sys/arch/armv7/dev/com_fdt.c
@@ -20,6 +20,7 @@
#include <sys/device.h>
#include <sys/tty.h>
+#define COM_CONSOLE /* ugly, i know. trigger for "a4x-bs-hack" */
#include <machine/intr.h>
#include <machine/bus.h>
#include <machine/fdt.h>
@@ -134,7 +135,11 @@ com_fdt_attach(struct device *parent, struct device *self,
void *aux)
* XXX This sucks. We need to get rid of the a4x bus tag
* altogether. For this we will need to change com(4).
*/
+#ifdef BUS_SPACE_OLD
sc->sc_iot = armv7_a4x_bs_tag;
+#else
+ sc->sc_iot = mainbus_bustag;
+#endif
sc->sc_iot.bs_cookie = faa->fa_iot->bs_cookie;
sc->sc_iot.bs_map = faa->fa_iot->bs_map;
diff --git a/sys/arch/armv7/dev/pluart.c b/sys/arch/armv7/dev/pluart.c
index cc03430bacb..56f9791ec7d 100644
--- a/sys/arch/armv7/dev/pluart.c
+++ b/sys/arch/armv7/dev/pluart.c
@@ -217,7 +217,7 @@ pluart_init_cons(void)
if (fdt_get_reg(node, 0, ®))
return;
- pluartcnattach(&armv7_bs_tag, reg.addr, comcnspeed, comcnmode);
+ pluartcnattach(&mainbus_bustag, reg.addr, comcnspeed, comcnmode);
}
int
diff --git a/sys/arch/armv7/exynos/exuart.c b/sys/arch/armv7/exynos/exuart.c
index aaea9a7cca3..bb82953ece7 100644
--- a/sys/arch/armv7/exynos/exuart.c
+++ b/sys/arch/armv7/exynos/exuart.c
@@ -155,7 +155,7 @@ exuart_init_cons(void)
if (fdt_get_reg(node, 0, ®))
return;
- exuartcnattach(&armv7_bs_tag, reg.addr, comcnspeed, comcnmode);
+ exuartcnattach(&mainbus_bustag, reg.addr, comcnspeed, comcnmode);
}
int
diff --git a/sys/arch/armv7/imx/imxuart.c b/sys/arch/armv7/imx/imxuart.c
index 1b460568b06..c78a9dc3803 100644
--- a/sys/arch/armv7/imx/imxuart.c
+++ b/sys/arch/armv7/imx/imxuart.c
@@ -145,7 +145,7 @@ imxuart_init_cons(void)
if (fdt_get_reg(node, 0, ®))
return;
- imxuartcnattach(&armv7_bs_tag, reg.addr, comcnspeed, comcnmode);
+ imxuartcnattach(&mainbus_bustag, reg.addr, comcnspeed, comcnmode);
}
int
diff --git a/sys/arch/armv7/include/bus.h b/sys/arch/armv7/include/bus.h
index ed737761885..b70f327ef49 100644
--- a/sys/arch/armv7/include/bus.h
+++ b/sys/arch/armv7/include/bus.h
@@ -1,4 +1,723 @@
/* $OpenBSD: bus.h,v 1.1 2013/09/04 14:38:26 patrick Exp $ */
/* $NetBSD: bus.h,v 1.3 2001/11/25 15:55:55 thorpej Exp $ */
+/*
+ * Copyright (c) 2004, Miodrag Vallat.
+ * Copyright (c) 2017 Artturi Alm.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Simple ARMv7 bus_space and bus_dma implementation.
+ * XXX bus_dma is the same old.
+ *
+ * Currently, we only need specific handling for 32 bit read/writes in D16
+ * space XXX, and this choice is made at compile time. As a result, all the
+ * implementation can go through macros or inline functions, except for
+ * the management functions.
+ */
+
+#ifndef _MACHINE_BUS_H_
+#define _MACHINE_BUS_H_
+
+#if defined(BUS_SPACE_OLD)
#include <arm/bus.h>
+#else
+
+#include <sys/types.h>
+
+/*
+ * 'neat' a4x-space hack..
+ * "too much MD" to include .h w/addresses<<2 in com.c (o_O), oh well.
+ */
+#ifdef COM_CONSOLE
+#define _ARMV7BUS_A4X_
+#endif
+#ifdef _ARMV7BUS_A4X_
+#define _bs_off(o) ((o) << 2)
+#else
+#define _bs_off(o) (o)
+#endif /* _ARMV7BUS_A4X_ */
+
+#define _cpu_dsb() asm volatile("dsb sy\n")
+#define _cpu_isb() asm volatile("isb sy\n")
+
+typedef u_long bus_addr_t;
+typedef u_long bus_size_t;
+
+typedef u_long bus_space_handle_t;
+
+#define BUS_SPACE_BARRIER_READ 0x01
+#define BUS_SPACE_BARRIER_WRITE 0x02
+
+#define BUS_SPACE_MAP_CACHEABLE 0x01
+#define BUS_SPACE_MAP_LINEAR 0x02
+#define BUS_SPACE_MAP_PREFETCHABLE 0x04
+
+
+/*
+ * General bus_space function set
+ */
+
+typedef struct bus_space {
+ int (*bs_map)(bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *);
+ void (*bs_unmap)(bus_space_handle_t, bus_size_t);
+} *bus_space_tag_t;
+
+
+#define bus_space_map(t,a,s,f,r) ((t)->bs_map(a,s,f,r))
+#define bus_space_unmap(t,h,s) ((t)->bs_unmap(h,s))
+static inline int bus_space_subregion(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, bus_size_t, bus_space_handle_t *);
+static inline void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t);
+static inline void bus_space_barrier(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, bus_size_t, int);
+
+int
+bus_space_subregion(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, bus_size_t size, bus_space_handle_t *ret)
+{
+ *ret = handle + offset;
+ return 0;
+}
+
+void *
+bus_space_vaddr(bus_space_tag_t tag, bus_space_handle_t handle)
+{
+ return (void *)handle;
+}
+
+void
+bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, bus_size_t size, int flags)
+{
+ _cpu_dsb();
+ _cpu_isb(); /* overkill? */
+}
+
+#define _bus_space_read_1(tag, handle, offset)
\
+ ((void)(tag), *(volatile u_int8_t *)((handle) + (offset)))
+#define _bus_space_read_2(tag, handle, offset)
\
+ ((void)(tag), *(volatile u_int16_t *)((handle) + (offset)))
+#define _bus_space_read_4(tag, handle, offset)
\
+ ((void)(tag), *(volatile u_int32_t *)((handle) + (offset)))
+
+#define _bus_space_write_1(tag, hdl, off, val) \
+ ((void)(tag), *(volatile u_int8_t *)((hdl) + (off)) = (val))
+#define _bus_space_write_2(tag, hdl, off, val) \
+ ((void)(tag), *(volatile u_int16_t *)((hdl) + (off)) = (val))
+#define _bus_space_write_4(tag, hdl, off, val) \
+ ((void)(tag), *(volatile u_int32_t *)((hdl) + (off)) = (val))
+
+
+/*
+ * Read/Write/Region functions.
+ * Most of these are straightforward and assume that everything is properly
+ * aligned.
+ */
+static inline uint8_t bus_space_read_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t);
+static inline uint16_t bus_space_read_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t);
+static inline uint32_t bus_space_read_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t);
+
+
+static inline void bus_space_read_multi_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int8_t *, size_t);
+static inline void bus_space_read_multi_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int16_t *, size_t);
+static inline void bus_space_read_multi_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int32_t *, size_t);
+
+
+static inline void bus_space_read_raw_multi_2(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+static inline void bus_space_read_raw_multi_4(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+
+
+static inline void bus_space_read_region_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int8_t *, size_t);
+static inline void bus_space_read_region_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int16_t *, size_t);
+static inline void bus_space_read_region_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int32_t *, size_t);
+
+
+static inline void bus_space_read_raw_region_2(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+static inline void bus_space_read_raw_region_4(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+
+
+static inline void bus_space_write_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, uint8_t);
+static inline void bus_space_write_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, uint16_t);
+static inline void bus_space_write_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, uint32_t);
+
+
+static inline void bus_space_write_multi_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, uint8_t *, size_t);
+static inline void bus_space_write_multi_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, uint16_t *, size_t);
+static inline void bus_space_write_multi_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, uint32_t *, size_t);
+
+
+static inline void bus_space_write_raw_multi_2(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, uint8_t *, size_t);
+static inline void bus_space_write_raw_multi_4(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+
+
+static inline void bus_space_set_multi_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int8_t, size_t);
+static inline void bus_space_set_multi_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int16_t, size_t);
+static inline void bus_space_set_multi_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int32_t, size_t);
+
+
+static inline void bus_space_write_region_1(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+static inline void bus_space_write_region_2(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int16_t *, size_t);
+static inline void bus_space_write_region_4(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int32_t *, size_t);
+
+
+static inline void bus_space_write_raw_region_2(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+static inline void bus_space_write_raw_region_4(bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t, u_int8_t *, size_t);
+
+
+static inline void bus_space_set_region_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int8_t, size_t);
+static inline void bus_space_set_region_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int16_t, size_t);
+static inline void bus_space_set_region_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, u_int32_t, size_t);
+
+
+static inline void bus_space_copy_1(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, bus_space_handle_t, bus_addr_t, bus_size_t);
+static inline void bus_space_copy_2(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, bus_space_handle_t, bus_addr_t, bus_size_t);
+static inline void bus_space_copy_4(bus_space_tag_t, bus_space_handle_t,
+ bus_addr_t, bus_space_handle_t, bus_addr_t, bus_size_t);
+
+
+/*
+ * read 1/2/4
+ */
+uint8_t
+bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset)
+{
+ _cpu_dsb();
+ return _bus_space_read_1(tag, handle, _bs_off(offset));
+}
+uint16_t
+bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset)
+{
+ _cpu_dsb();
+ return _bus_space_read_2(tag, handle, _bs_off(offset));
+}
+uint32_t
+bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset)
+{
+ _cpu_dsb();
+ return _bus_space_read_4(tag, handle, _bs_off(offset));
+}
+
+
+/*
+ * read multi 1/2/4
+ */
+void
+bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ *dest++ = _bus_space_read_1(tag, handle, offset);
+ _cpu_dsb();
+}
+void
+bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int16_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ *dest++ = _bus_space_read_2(tag, handle, offset);
+ _cpu_dsb();
+}
+void
+bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ *dest++ = _bus_space_read_4(tag, handle, offset);
+ _cpu_dsb();
+}
+
+
+/*
+ * read raw multi 2/4
+ */
+void
+bus_space_read_raw_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 1;
+ while ((int)--size >= 0) {
+ *(u_int16_t *)dest =
+ _bus_space_read_2(tag, handle, offset);
+ dest += 2;
+ }
+ _cpu_dsb();
+}
+void
+bus_space_read_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 2;
+ while ((int)--size >= 0) {
+ *(u_int32_t *)dest =
+ _bus_space_read_4(tag, handle, offset);
+ dest += 4;
+ }
+ _cpu_dsb();
+}
+
+
+/*
+ * read region 1/2/4
+ */
+void
+bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ *dest++ = _bus_space_read_1(tag, handle, offset++);
+ _cpu_dsb();
+}
+void
+bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int16_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0) {
+ *dest++ = _bus_space_read_2(tag, handle, offset);
+ offset += 2;
+ }
+ _cpu_dsb();
+}
+void
+bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0) {
+ *dest++ = _bus_space_read_4(tag, handle, offset);
+ offset += 4;
+ }
+ _cpu_dsb();
+}
+
+
+/*
+ * read raw region 2/4
+ */
+void
+bus_space_read_raw_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 1;
+ while ((int)--size >= 0) {
+ *(u_int16_t *)dest = _bus_space_read_2(tag, handle, offset);
+ offset += 2;
+ dest += 2;
+ }
+ _cpu_dsb();
+}
+void
+bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 2;
+ while ((int)--size >= 0) {
+ *(u_int32_t *)dest = _bus_space_read_4(tag, handle, offset);
+ offset += 4;
+ dest += 4;
+ }
+ _cpu_dsb();
+}
+
+
+/*
+ * write 1/2/4
+ */
+void
+bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, uint8_t value)
+{
+ _bus_space_write_1(tag, handle, _bs_off(offset), value);
+ _cpu_dsb();
+}
+void
+bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, uint16_t value)
+{
+ _bus_space_write_2(tag, handle, _bs_off(offset), value);
+ _cpu_dsb();
+}
+void
+bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, uint32_t value)
+{
+ _bus_space_write_4(tag, handle, _bs_off(offset), value);
+ _cpu_dsb();
+}
+
+
+/*
+ * write multi 1/2/4
+ */
+void
+bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, uint8_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_1(tag, handle, offset, *dest++);
+ _cpu_dsb();
+}
+void
+bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, uint16_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_2(tag, handle, offset, *dest++);
+ _cpu_dsb();
+}
+void
+bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, uint32_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_4(tag, handle, offset, *dest++);
+ _cpu_dsb();
+}
+
+
+/*
+ * write raw multi 2/4
+ */
+void
+bus_space_write_raw_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, uint8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 1;
+ while ((int)--size >= 0) {
+ _bus_space_write_2(tag, handle, offset, *(uint16_t *)dest);
+ dest += 2;
+ }
+ _cpu_dsb();
+}
+void
+bus_space_write_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 2;
+ while ((int)--size >= 0) {
+ _bus_space_write_4(tag, handle, offset, *(u_int32_t *)dest);
+ dest += 4;
+ }
+ _cpu_dsb();
+}
+
+
+/*
+ * set multi 1/2/4
+ */
+void
+bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t value, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_1(tag, handle, offset, value);
+ _cpu_dsb();
+}
+void
+bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int16_t value, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_2(tag, handle, offset, value);
+ _cpu_dsb();
+}
+void
+bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int32_t value, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_4(tag, handle, offset, value);
+ _cpu_dsb();
+}
+
+
+/*
+ * write region 1/2/4
+ */
+void
+bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_1(tag, handle, offset++, *dest++);
+ _cpu_dsb();
+}
+void
+bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int16_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0) {
+ _bus_space_write_2(tag, handle, offset, *dest++);
+ offset += 2;
+ }
+ _cpu_dsb();
+}
+void
+bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0) {
+ _bus_space_write_4(tag, handle, offset, *dest++);
+ offset += 4;
+ }
+ _cpu_dsb();
+}
+
+
+/*
+ * write raw region 2/4
+ */
+void
+bus_space_write_raw_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 1;
+ while ((int)--size >= 0) {
+ _bus_space_write_2(tag, handle, offset, *(u_int16_t *)dest);
+ offset += 2;
+ dest += 2;
+ }
+ _cpu_dsb();
+}
+void
+bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+ offset = _bs_off(offset);
+ size >>= 2;
+ while ((int)--size >= 0) {
+ _bus_space_write_4(tag, handle, offset, *(u_int32_t *)dest);
+ offset += 4;
+ dest += 4;
+ }
+ _cpu_dsb();
+}
+
+
+/*
+ * set region 1/2/4
+ */
+void
+bus_space_set_region_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int8_t value, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0)
+ _bus_space_write_1(tag, handle, offset++, value);
+ _cpu_dsb();
+}
+void
+bus_space_set_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int16_t value, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0) {
+ _bus_space_write_2(tag, handle, offset, value);
+ offset += 2;
+ }
+ _cpu_dsb();
+}
+void
+bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_addr_t offset, u_int32_t value, size_t count)
+{
+ offset = _bs_off(offset);
+ while ((int)--count >= 0) {
+ _bus_space_write_4(tag, handle, offset, value);
+ offset += 4;
+ }
+ _cpu_dsb();
+}
+
+
+/*
+ * copy 1/2/4
+ */
+void
+bus_space_copy_1(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1,
+ bus_space_handle_t h2, bus_addr_t o2, bus_size_t count)
+{
+ o1 = h1 + _bs_off(o1);
+ o2 = h2 + _bs_off(o2);
+ while ((int)--count >= 0) {
+ *(volatile u_int8_t *)o1 = *(volatile u_int8_t *)o2;
+ _cpu_dsb();
+ o1++;
+ o2++;
+ }
+}
+void
+bus_space_copy_2(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1,
+ bus_space_handle_t h2, bus_addr_t o2, bus_size_t count)
+{
+ o1 = h1 + _bs_off(o1);
+ o2 = h2 + _bs_off(o2);
+ while ((int)--count >= 0) {
+ *(volatile u_int16_t *)o1 = *(volatile u_int16_t *)o2;
+ _cpu_dsb();
+ o1 += 2;
+ o2 += 2;
+ }
+}
+void
+bus_space_copy_4(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1,
+ bus_space_handle_t h2, bus_addr_t o2, bus_size_t count)
+{
+ o1 = h1 + _bs_off(o1);
+ o2 = h2 + _bs_off(o2);
+ while ((int)--count >= 0) {
+ *(volatile u_int32_t *)o1 = *(volatile u_int32_t *)o2;
+ _cpu_dsb();
+ o1 += 4;
+ o2 += 4;
+ }
+}
+
+#include <arm/bus_dma.h>
+
+#if /* XXX */0
+/* These are OpenBSD extensions to the general NetBSD bus interface. */
+void
+bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, u_int8_t *dst, bus_size_t size);
+void
+bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, u_int8_t *dst, bus_size_t size);
+#define bus_space_read_raw_multi_8 \
+ !!! bus_space_read_raw_multi_8 not implemented !!!
+
+void
+bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, const u_int8_t *src, bus_size_t size);
+void
+bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_addr_t ba, const u_int8_t *src, bus_size_t size);
+#define bus_space_write_raw_multi_8 \
+ !!! bus_space_write_raw_multi_8 not implemented !!!
+
+/*
+ * void bus_space_read_raw_region_N(bus_space_tag_t tag,
+ * bus_space_handle_t bsh, bus_size_t offset,
+ * u_int8_t *addr, size_t count);
+ *
+ * Read `count' bytes in 2, 4 or 8 byte wide quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided. The buffer must have proper alignment for the N byte
+ * wide entities. Furthermore possible byte-swapping should be done by
+ * these functions.
+ */
+
+#define bus_space_read_raw_region_2(t, h, o, a, c) \
+ bus_space_read_region_2((t), (h), (o), (u_int16_t *)(a), (c) >> 1)
+#define bus_space_read_raw_region_4(t, h, o, a, c) \
+ bus_space_read_region_4((t), (h), (o), (u_int32_t *)(a), (c) >> 2)
+
+#if 0 /* Cause a link error for bus_space_read_raw_region_8 */
+#define bus_space_read_raw_region_8 \
+ !!! bus_space_read_raw_region_8 unimplemented !!!
+#endif
+
+/*
+ * void bus_space_write_raw_region_N(bus_space_tag_t tag,
+ * bus_space_handle_t bsh, bus_size_t offset,
+ * const u_int8_t *addr, size_t count);
+ *
+ * Write `count' bytes in 2, 4 or 8 byte wide quantities to bus space
+ * described by tag/handle and starting at `offset' from the
+ * buffer provided. The buffer must have proper alignment for the N byte
+ * wide entities. Furthermore possible byte-swapping should be done by
+ * these functions.
+ */
+
+#define bus_space_write_raw_region_2(t, h, o, a, c) \
+ bus_space_write_region_2((t), (h), (o), (const u_int16_t *)(a), (c) >> 1)
+#define bus_space_write_raw_region_4(t, h, o, a, c) \
+ bus_space_write_region_4((t), (h), (o), (const u_int32_t *)(a), (c) >> 2)
+
+#if 0 /* Cause a link error for bus_space_write_raw_region_8 */
+#define bus_space_write_raw_region_8 \
+ !!! bus_space_write_raw_region_8 unimplemented !!!
+#endif
+#endif
+
+#endif /* !ARM_BUS */
+#endif /* _MACHINE_BUS_H_ */
diff --git a/sys/arch/armv7/omap/intc.c b/sys/arch/armv7/omap/intc.c
index a68a5be5741..de0e6090f8e 100644
--- a/sys/arch/armv7/omap/intc.c
+++ b/sys/arch/armv7/omap/intc.c
@@ -314,8 +314,7 @@ void
intc_intr_bootstrap(vaddr_t addr)
{
int i, j;
- extern struct bus_space armv7_bs_tag;
- intc_iot = &armv7_bs_tag;
+ intc_iot = &mainbus_bustag;
intc_ioh = addr;
for (i = 0; i < INTC_NUM_BANKS; i++)
for (j = 0; j < NIPL; j++)
diff --git a/sys/dev/ic/com.c b/sys/dev/ic/com.c
index ba3dfce322a..a9543b5938b 100644
--- a/sys/dev/ic/com.c
+++ b/sys/dev/ic/com.c
@@ -78,10 +78,10 @@
#include <ddb/db_var.h>
#endif
+#define COM_CONSOLE
#include <machine/bus.h>
#include <machine/intr.h>
-#define COM_CONSOLE
#include <dev/cons.h>
#include <dev/ic/comreg.h>
