> Date: Wed, 5 Jul 2017 09:34:59 +0300
> From: Artturi Alm <artturi....@gmail.com>
>
> On Wed, Jul 05, 2017 at 02:27:46AM +0300, Artturi Alm wrote:
> > Hi,
> >
> > instead of messing w/bs_tags, use the fact pmap_kernel()->pm_refs is going
> > to be 0 until pmap_bootstrap() has ran. tmp_bs_tag was unused, and
> > bootstrap_bs_map doesn't need/use the void *t-arg when being ran indirectly
> > via armv7_bs_map().
> >
> > the whole existence of bootstrap_bs_map is another story, and the comment in
> > /* Now, map the FDT area. */ is somewhat an stupid excuse, it's already
> > mapped
> > before initarm() w/VA=PA, and could well be _init()&_get_size()'d &
> > memcpy'ed
> > somewhere in reach within bootstrap KVA, guess diff might follow for that,
> > too, if anyone has time for these simplifications.
> >
>
> Ok, i was wrong ^there, and the bootstrap code before initarm() didn't fill
> the L1 w/VA=PA anymore, for reasons i don't understand, so i 'fixed' it,
> with diff below. tested to boot and eeprom -p normally on cubie2 and wandb.
>
> i kept the diff minimal, to the point it does fdt_get_size() twice just like
> before, which i don't like, nor the name of size-variable and what not, but
> minimal it is. Would be the first step towards earlier physmem load :)
>
> -Artturi
What are you trying to achieve heree?
The current code quite deliberately does not create a cachable 1:1
mapping for the entire address space. Such a mapping is dangerous as
the CPU might speculatively load from any valid mapping and that is a
terrible idea for device mappings.
> diff --git a/sys/arch/armv7/armv7/armv7_machdep.c
> b/sys/arch/armv7/armv7/armv7_machdep.c
> index aa1c549b29b..3b860cc662f 100644
> --- a/sys/arch/armv7/armv7/armv7_machdep.c
> +++ b/sys/arch/armv7/armv7/armv7_machdep.c
> @@ -379,7 +379,7 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
> loadaddr)
> paddr_t memstart;
> psize_t memsize;
> paddr_t memend;
> - void *config;
> + void *config = arg2;
> size_t size;
> void *node;
> extern uint32_t esym; /* &_end if no symbols are loaded */
> @@ -420,18 +420,8 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
> loadaddr)
> tmp_bs_tag.bs_map = bootstrap_bs_map;
>
> /*
> - * Now, map the FDT area.
> - *
> - * As we don't know the size of a possible FDT, map the size of a
> - * typical bootstrap bs map. The FDT might not be aligned, so this
> - * might take up to two L1_S_SIZEd mappings.
> - *
> - * XXX: There's (currently) no way to unmap a bootstrap mapping, so
> - * we might lose a bit of the bootstrap address space.
> + * Now, init the FDT @ PA, reloc and reinit to KVA later.
> */
> - bootstrap_bs_map(NULL, (bus_addr_t)arg2, L1_S_SIZE, 0,
> - (bus_space_handle_t *)&config);
> -
> if (!fdt_init(config) || fdt_get_size(config) == 0)
> panic("initarm: no FDT");
>
> @@ -572,11 +562,15 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
> loadaddr)
> #endif
>
> /*
> - * Allocate pages for an FDT copy.
> + * Allocate pages for FDT, copy it there, and zero the original.
> */
> size = fdt_get_size(config);
> valloc_pages(fdt, round_page(size) / PAGE_SIZE);
> memcpy((void *)fdt.pv_pa, config, size);
> + memset(config, 0, size);
> +
> + /* Now we must reinit the FDT, using the virtual address. */
> + fdt_init((void *)fdt.pv_va);
>
> /*
> * XXX Defer this to later so that we can reclaim the memory
> @@ -726,9 +720,6 @@ initarm(void *arg0, void *arg1, void *arg2, paddr_t
> loadaddr)
> prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
> undefined_handler_address = (u_int)undefinedinstruction_bounce;
>
> - /* Now we can reinit the FDT, using the virtual address. */
> - fdt_init((void *)fdt.pv_va);
> -
> /* Initialise the undefined instruction handlers */
> #ifdef VERBOSE_INIT_ARM
> printf("undefined ");
> diff --git a/sys/arch/armv7/armv7/locore0.S b/sys/arch/armv7/armv7/locore0.S
> index 2a4e98cbe8c..5fc7d250cf5 100644
> --- a/sys/arch/armv7/armv7/locore0.S
> +++ b/sys/arch/armv7/armv7/locore0.S
> @@ -127,19 +127,9 @@ _C_LABEL(bootstrap_start):
> bne 2b
>
> adr r4, mmu_init_table
> -
> - mov r2, r9, lsr #18
> - ldr r3, [r4, #8]
> - bic r3, r3, #0xf0000000
> - orr r3, r3, r9
> - str r2, [r4, #4]
> - str r3, [r4, #8]
> - str r3, [r4, #0x14] // ram address for 0xc0000000
> -
> - /*
> - * the first entry has two fields that need to be updated for
> - * specific ram configuration of this board.
> - */
> + ldr r3, [r4, #(12+8)] /* r3 = pte attributes */
> + orr r3, r3, r9 /* r3 |= pa */
> + str r3, [r4, #(12+8)] /* ram address(PA) for 0xc0000000 */
> b 4f
>
> 3:
> @@ -186,7 +176,7 @@ Lstart:
>
> mmu_init_table:
> /* map SDRAM VA==PA, WT cacheable */
> - MMU_INIT(0x00000000, 0x00000000, 64,
> + MMU_INIT(0x00000000, 0x00000000, 4096,
> L1_TYPE_S|L1_S_C|L1_S_V7_AP(AP_KRW)|L1_S_V7_AF)
> /* map VA 0xc0000000..0xc3ffffff to PA */
> MMU_INIT(0xc0000000, 0x00000000, 64,
>
>
