Hi,
might have sent this before. at best (or worst, depends how you look at
things), these could help hide a bug that'd be able to bring everything
down in flames, altho. i'm not suggesting so, and have in the past ran
w/asserts to make sure these were invariant, fwiw., now there is more
of rather pointless variables there, but only these come w/removal of
just a single if (... && <_nop_check>).
-Artturi
diff --git a/sys/arch/arm/arm/bus_dma.c b/sys/arch/arm/arm/bus_dma.c
index ce637651800..e1016e3c65c 100644
--- a/sys/arch/arm/arm/bus_dma.c
+++ b/sys/arch/arm/arm/bus_dma.c
@@ -749,8 +749,7 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map,
bus_addr_t offset,
* vmspace has not been active since the last time a full
* cache flush was performed, we don't need to do anything.
*/
- if (__predict_false(map->_dm_proc != NULL &&
- map->_dm_proc->p_vmspace->vm_map.pmap->pm_cstate.cs_cache_d == 0))
+ if (__predict_false(map->_dm_proc != NULL))
return;
switch (map->_dm_buftype) {
diff --git a/sys/arch/arm/arm/genassym.cf b/sys/arch/arm/arm/genassym.cf
index 3937b930c39..c6f6d097476 100644
--- a/sys/arch/arm/arm/genassym.cf
+++ b/sys/arch/arm/arm/genassym.cf
@@ -61,7 +61,6 @@ define __ARM_FIQ_INDIRECT 1
endif
export DOMAIN_CLIENT
-export PMAP_DOMAIN_KERNEL
ifdef PMAP_INCLUDE_PTE_SYNC
define PMAP_INCLUDE_PTE_SYNC 1
@@ -86,8 +85,6 @@ member pcb_tf
member pcb_pagedir
member pcb_pl1vec
member pcb_l1vec
-member pcb_dacr
-member pcb_cstate
member pcb_flags
member PCB_R8 pcb_un.un_32.pcb32_r8
member PCB_R9 pcb_un.un_32.pcb32_r9
@@ -112,18 +109,6 @@ struct vmspace
member vm_map
member VM_PMAP vm_map.pmap
-union pmap_cache_state
-member cs_tlb_id
-member cs_tlb_d
-member cs_tlb
-member cs_cache_id
-member cs_cache_d
-member cs_cache
-member cs_all
-
-struct pmap
-member PMAP_CSTATE pm_cstate
-
struct uprof
member pr_base
member pr_size
diff --git a/sys/arch/arm/include/pcb.h b/sys/arch/arm/include/pcb.h
index 1f63d2bf044..c90aca90436 100644
--- a/sys/arch/arm/include/pcb.h
+++ b/sys/arch/arm/include/pcb.h
@@ -48,8 +48,6 @@ struct pcb_arm32 {
paddr_t pcb32_pagedir; /* PT hooks */
pd_entry_t *pcb32_pl1vec; /* PTR to vector_base L1 entry*/
pd_entry_t pcb32_l1vec; /* Value to stuff on ctx sw */
- u_int pcb32_dacr; /* Domain Access Control Reg */
- void *pcb32_cstate; /* &pmap->pm_cstate */
/*
* WARNING!
* cpuswitch.S relies on pcb32_r8 being quad-aligned in struct pcb
@@ -68,8 +66,6 @@ struct pcb_arm32 {
#define pcb_pagedir pcb_un.un_32.pcb32_pagedir
#define pcb_pl1vec pcb_un.un_32.pcb32_pl1vec
#define pcb_l1vec pcb_un.un_32.pcb32_l1vec
-#define pcb_dacr pcb_un.un_32.pcb32_dacr
-#define pcb_cstate pcb_un.un_32.pcb32_cstate
/*
* WARNING!
diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h
index 83c3395f710..e1b0e0335fc 100644
--- a/sys/arch/arm/include/pmap.h
+++ b/sys/arch/arm/include/pmap.h
@@ -125,54 +125,11 @@ struct l1_ttable;
struct l2_dtable;
/*
- * Track cache/tlb occupancy using the following structure
- */
-union pmap_cache_state {
- struct {
- union {
- u_int8_t csu_cache_b[2];
- u_int16_t csu_cache;
- } cs_cache_u;
-
- union {
- u_int8_t csu_tlb_b[2];
- u_int16_t csu_tlb;
- } cs_tlb_u;
- } cs_s;
- u_int32_t cs_all;
-};
-#define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0]
-#define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1]
-#define cs_cache cs_s.cs_cache_u.csu_cache
-#define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0]
-#define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1]
-#define cs_tlb cs_s.cs_tlb_u.csu_tlb
-
-/*
- * Assigned to cs_all to force cacheops to work for a particular pmap
- */
-#define PMAP_CACHE_STATE_ALL 0xffffffffu
-
-/*
- * This structure is used by machine-dependent code to describe
- * static mappings of devices, created at bootstrap time.
- */
-struct pmap_devmap {
- vaddr_t pd_va; /* virtual address */
- paddr_t pd_pa; /* physical address */
- psize_t pd_size; /* size of region */
- vm_prot_t pd_prot; /* protection code */
- int pd_cache; /* cache attributes */
-};
-
-/*
* The pmap structure itself
*/
struct pmap {
- u_int8_t pm_domain;
boolean_t pm_remove_all;
struct l1_ttable *pm_l1;
- union pmap_cache_state pm_cstate;
u_int pm_refs;
struct l2_dtable *pm_l2[L2_SIZE];
struct pmap_statistics pm_stats;
@@ -274,16 +231,11 @@ void vector_page_setprot(int);
/* XXX */
void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable);
-const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
-const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
-
/* Bootstrapping routines. */
void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
-void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
-void pmap_devmap_register(const struct pmap_devmap *);
/*
* The current top of kernel VM
@@ -429,12 +381,6 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
/*****************************************************************************/
/*
- * Definitions for MMU domains
- */
-#define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */
-#define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */
-
-/*
* These macros define the various bit masks in the PTE.
*
* We use these macros since we use different bits on different processor
@@ -645,24 +591,12 @@ extern uint32_t pmap_alias_bits;
struct vm_page_md {
struct pv_entry *pvh_list; /* pv_entry list */
int pvh_attrs; /* page attributes */
- u_int uro_mappings;
- u_int urw_mappings;
- union {
- u_short s_mappings[2]; /* Assume kernel count <= 65535 */
- u_int i_mappings;
- } k_u;
-#define kro_mappings k_u.s_mappings[0]
-#define krw_mappings k_u.s_mappings[1]
-#define k_mappings k_u.i_mappings
};
#define VM_MDPAGE_INIT(pg)
\
do { \
(pg)->mdpage.pvh_list = NULL; \
(pg)->mdpage.pvh_attrs = 0; \
- (pg)->mdpage.uro_mappings = 0; \
- (pg)->mdpage.urw_mappings = 0; \
- (pg)->mdpage.k_mappings = 0; \
} while (/*CONSTCOND*/0)
#endif /* _LOCORE */
