On Fri, 24 Nov 2017 20:26:02 +0100 (CET)
> This device is based on the same Synopsys Designware "IP" as what's > found on many ARM SoCs. Pretty much com(4) compatible but with some > twists. > > 1. The registers are wider. Instead of the traditional 1-byte > registers it has 4-byte registers. On ARM we use a bus_space hack > to get around this issue, but I don't think I want to advocate > replicating that approach for amd64/i386. Abstracting the register > access functions is probably the way to go. > I wish I had a 32bit uart on ARM cortex, 16 bit is neither here nor there, though quite useful in some scenarios ;) You mean a shifting function with single byte I/O? > 2. There are additional registers. It seems that most of these can be > ignored, but the USR register needs to be poked under some > circumstances. See sys/arch/armv7/dev/conm_fdt.c. > Nice, I hadn't actually thought of looking at OpenBSD ARM. I was looking at: https://cateee.net/lkddb/web-lkddb/SERIAL_8250_LPSS.html https://github.com/torvalds/linux/blob/master/drivers/tty/serial/8250/8250_lpss.c > Also, are you looking at acpi attachment or straight PCI? I was thinking PCI mainly because It looks like from the dmesg that ACPI would also require a driver. Any thoughts? Thanks
