Additional AMD CPUID bits documented in
"Processor Programming Reference (PPR) for AMD Family 17h
Model 01h, Revision B1 Processors"
Index: i386/include/specialreg.h
===================================================================
RCS file: /cvs/src/sys/arch/i386/include/specialreg.h,v
retrieving revision 1.64
diff -u -p -r1.64 specialreg.h
--- i386/include/specialreg.h 12 Aug 2017 19:53:37 -0000 1.64
+++ i386/include/specialreg.h 9 Feb 2018 01:52:53 -0000
@@ -265,12 +265,17 @@
/* Reserved 0x00004000 */
#define CPUIDECX_LWP 0x00008000 /* Lightweight profiling
support */
#define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA
instructions */
-/* Reserved 0x00020000 */
+#define CPUIDECX_TCE 0x00020000 /* Translation Cache
Extension */
/* Reserved 0x00040000 */
#define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */
/* Reserved 0x00100000 */
#define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation
instruction */
#define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions
support */
+#define CPUIDECX_CPCTR 0x00800000 /* core performance counter
ext */
+#define CPUIDECX_DBKP 0x04000000 /* DataBreakpointExtension */
+#define CPUIDECX_PERFTSC 0x08000000 /* performance time-stamp
counter */
+#define CPUIDECX_PCTRL3 0x10000000 /* L3 performance counter
ext */
+#define CPUIDECX_MWAITX 0x20000000 /* MWAITX/MONITORX */
/*
* "Advanced Power Management Information" bits (CPUID function 0x80000007):
Index: i386/i386/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.609
diff -u -p -r1.609 machdep.c
--- i386/i386/machdep.c 22 Jan 2018 09:08:43 -0000 1.609
+++ i386/i386/machdep.c 9 Feb 2018 01:52:54 -0000
@@ -1017,9 +1017,15 @@ const struct cpu_cpuid_feature i386_ecpu
{ CPUIDECX_WDT, "WDT" },
{ CPUIDECX_LWP, "LWP" },
{ CPUIDECX_FMA4, "FMA4" },
+ { CPUIDECX_TCE, "TCE" },
{ CPUIDECX_NODEID, "NODEID" },
{ CPUIDECX_TBM, "TBM" },
{ CPUIDECX_TOPEXT, "TOPEXT" },
+ { CPUIDECX_CPCTR, "CPCTR" },
+ { CPUIDECX_DBKP, "DBKP" },
+ { CPUIDECX_PERFTSC, "PERFTSC" },
+ { CPUIDECX_PCTRL3, "PCTRL3" },
+ { CPUIDECX_MWAITX, "MWAITX" },
};
const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = {
Index: amd64/include/specialreg.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/specialreg.h,v
retrieving revision 1.66
diff -u -p -r1.66 specialreg.h
--- amd64/include/specialreg.h 15 Jan 2018 18:57:59 -0000 1.66
+++ amd64/include/specialreg.h 9 Feb 2018 01:52:54 -0000
@@ -279,12 +279,17 @@
/* Reserved 0x00004000 */
#define CPUIDECX_LWP 0x00008000 /* Lightweight profiling
support */
#define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA
instructions */
-/* Reserved 0x00020000 */
+#define CPUIDECX_TCE 0x00020000 /* Translation Cache
Extension */
/* Reserved 0x00040000 */
#define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */
/* Reserved 0x00100000 */
#define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation
instruction */
#define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions
support */
+#define CPUIDECX_CPCTR 0x00800000 /* core performance counter
ext */
+#define CPUIDECX_DBKP 0x04000000 /* DataBreakpointExtension */
+#define CPUIDECX_PERFTSC 0x08000000 /* performance time-stamp
counter */
+#define CPUIDECX_PCTRL3 0x10000000 /* L3 performance counter
ext */
+#define CPUIDECX_MWAITX 0x20000000 /* MWAITX/MONITORX */
/*
* "Advanced Power Management Information" bits (CPUID function 0x80000007):
Index: amd64/amd64/identcpu.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/identcpu.c,v
retrieving revision 1.93
diff -u -p -r1.93 identcpu.c
--- amd64/amd64/identcpu.c 15 Jan 2018 06:53:02 -0000 1.93
+++ amd64/amd64/identcpu.c 9 Feb 2018 01:52:54 -0000
@@ -160,9 +160,15 @@ const struct {
{ CPUIDECX_SKINIT, "SKINIT" },
{ CPUIDECX_LWP, "WDT" },
{ CPUIDECX_FMA4, "FMA4" },
+ { CPUIDECX_TCE, "TCE" },
{ CPUIDECX_NODEID, "NODEID" },
{ CPUIDECX_TBM, "TBM" },
{ CPUIDECX_TOPEXT, "TOPEXT" },
+ { CPUIDECX_CPCTR, "CPCTR" },
+ { CPUIDECX_DBKP, "DBKP" },
+ { CPUIDECX_PERFTSC, "PERFTSC" },
+ { CPUIDECX_PCTRL3, "PCTRL3" },
+ { CPUIDECX_MWAITX, "MWAITX" },
}, cpu_seff0_ebxfeatures[] = {
{ SEFF0EBX_FSGSBASE, "FSGSBASE" },
{ SEFF0EBX_SGX, "SGX" },
