In the intel_gtt_chipset_setup() routine, called at initialization,
the driver maps pci space for certain chip models only, but later in
intel_gtt_chipset_flush() it calls bus_space_write() on it in cases
it's not initialized.
This results in crashes during boot with "Pineview" generation chips,
which are "gen == 3", but, according to intel_gtt_chipset_setup() have
no flush page mechanism.
Fix this by adding a flag indicating whether the feature is available
or not. Then use the flag to check if it's OK to write to the pci
space. This is the what the driver did before the 14 april update.
OK?
FWIW, first it looked surprising to do nothing in
intel_gtt_chipset_flush(), so I also tried to call the "gen < 3"
code. It works as well.
Index: intel_gtt.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_gtt.c,v
retrieving revision 1.2
diff -u -p -u -p -r1.2 intel_gtt.c
--- intel_gtt.c 14 Apr 2019 10:14:52 -0000 1.2
+++ intel_gtt.c 9 May 2019 05:37:09 -0000
@@ -120,6 +120,8 @@ intel_gtt_chipset_setup(struct drm_devic
struct inteldrm_softc *dev_priv = dev->dev_private;
struct pci_attach_args bpa;
+ dev_priv->has_ifp = 0;
+
if (INTEL_GEN(dev_priv) >= 6)
return;
@@ -133,8 +135,10 @@ intel_gtt_chipset_setup(struct drm_devic
if (IS_I915G(dev_priv) || IS_I915GM(dev_priv) || IS_I945G(dev_priv) ||
IS_I945GM(dev_priv)) {
i915_alloc_ifp(dev_priv, &bpa);
+ dev_priv->has_ifp = 1;
} else if (INTEL_GEN(dev_priv) >= 4 || IS_G33(dev_priv)) {
i965_alloc_ifp(dev_priv, &bpa);
+ dev_priv->has_ifp = 1;
} else {
int nsegs;
/*
@@ -192,7 +196,7 @@ intel_gtt_chipset_flush(void)
* The write will return when it is done.
*/
if (INTEL_GEN(dev_priv) >= 3) {
- if (dev_priv->ifp.i9xx.bsh != 0)
+ if (dev_priv->has_ifp && dev_priv->ifp.i9xx.bsh != 0)
bus_space_write_4(dev_priv->ifp.i9xx.bst,
dev_priv->ifp.i9xx.bsh, 0, 1);
} else {
