On Fri, Feb 14, 2020 at 06:28:20PM +0100, Martin Pieuchot wrote: > This diff introduces the concept of "queue" in the em(4) driver. The > logic present in ix(4) has been matched for coherency. > > Currently the driver uses a single queue and the diff below doesn't > change anything in that regard. It can be viewed as the introduction > of an abstraction. > > I'd like to get this in to reduce the differences between em(4) and > ix(4) when it comes to multiqueues. My intend is to keep the upcoming > changes as small as possible such that we can concentrate our efforts on > the important bits. So far we started discussing the interaction between > CPU and mapping MSIX vectors but other related topics will appear :o) > > I'm running this on: > > em0 at pci1 dev 0 function 0 "Intel I210" rev 0x03: msi > em0 at pci0 dev 20 function 0 "Intel I354 SGMII" rev 0x03: msi > > More tests are always welcome ;)
I can test this on some other hardware tomorrow. I read through it and it all makes sense to me. One question below, but ok jmatthew@ > @@ -2597,13 +2635,6 @@ em_initialize_receive_unit(struct em_sof > E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); > } > > - /* Setup the Base and Length of the Rx Descriptor Ring */ > - bus_addr = sc->sc_rx_dma.dma_map->dm_segs[0].ds_addr; > - E1000_WRITE_REG(&sc->hw, RDLEN(0), > - sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); > - E1000_WRITE_REG(&sc->hw, RDBAH(0), (u_int32_t)(bus_addr >> 32)); > - E1000_WRITE_REG(&sc->hw, RDBAL(0), (u_int32_t)bus_addr); > - > /* Setup the Receive Control Register */ > reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | > E1000_RCTL_RDMTS_HALF | > @@ -2653,6 +2684,13 @@ em_initialize_receive_unit(struct em_sof > if (sc->hw.mac_type == em_82573) > E1000_WRITE_REG(&sc->hw, RDTR, 0x20); > > + /* Setup the Base and Length of the Rx Descriptor Ring */ > + bus_addr = que->rx.sc_rx_dma.dma_map->dm_segs[0].ds_addr; > + E1000_WRITE_REG(&sc->hw, RDLEN(0), > + sc->sc_rx_slots * sizeof(*que->rx.sc_rx_desc_ring)); > + E1000_WRITE_REG(&sc->hw, RDBAH(0), (u_int32_t)(bus_addr >> 32)); > + E1000_WRITE_REG(&sc->hw, RDBAL(0), (u_int32_t)bus_addr); > + Just to make sure that I follow how this works, should we be setting RDLEN(que->me) rather than RDLEN(0) here, and likewise for RDBAH and RDBAL? This value is always 0 at this stage, so of course it doesn't matter yet.
