I've always interpreted the bit of code that takes the bus number from
_CRS instead of _BBN, ut allegedly this is not how it works and _BBN
is supposedly only there to make sure we can access PCI config space
of the host bridge from AML code.
Fortunately having _CRS provide the bus number is just a one-line
diff. This might fix PCIe on the Honeycomb LX2K which is a 16-core
"workstation" mini-ITX board based on NXP's LX2160A board made bu
SolidRun. I'd like to have this in 6.7. Tested on the Ampere machine
and the od1000 in ACPI mode.
ok?
Index: arch/arm64/dev/acpipci.c
===================================================================
RCS file: /cvs/src/sys/arch/arm64/dev/acpipci.c,v
retrieving revision 1.13
diff -u -p -r1.13 acpipci.c
--- arch/arm64/dev/acpipci.c 22 Aug 2019 17:14:21 -0000 1.13
+++ arch/arm64/dev/acpipci.c 2 May 2020 12:21:24 -0000
@@ -268,6 +268,10 @@ acpipci_parse_resources(int crsidx, unio
break;
case LR_TYPE_BUS:
extent_free(sc->sc_busex, min, len, EX_WAITOK);
+ /*
+ * Let _CRS minimum bus number override _BBN.
+ */
+ sc->sc_bus = min;
break;
}
