> From: James Hastings <[email protected]>
> Date: Tue, 3 Nov 2020 22:58:04 -0500 (EST)
>
> On 10/14/20, Mark Kettenis <[email protected]> wrote:
> >> From: James Hastings <[email protected]>
> >> Date: Sun, 11 Oct 2020 03:49:11 -0400 (EDT)
> >>
> >> On Thu, 08 Oct 2020 20:29:38 +0000 Mark Kettenis wrote:
> >> > Diff below adds a driver for the GPIO controller found on the Intel
> >> > 400 Series PCH as found on (for example) the Lenovo X1 gen 8 laptop.
> >> > Since I don't have such hardware, I'd appreciate some tests on laptops
> >> > that current show:
> >> >
> >> > "INT34BB" at acpi0 not configured
> >> >
> >>
> >> Thanks for the driver Mark! Compiles fine here but panics like this:
> >> ihidev0 at iic0 addr 0x2c gpio 291panic: kernel diagnostic assertion "pin
> >> >= 0 && pin < sc->sc_npins" failed: file
> >> "/usr/src/sys/dev/acpi/pchgpio.c", line 335
> >>
> >> Let me know any way I can help.
> >
> > Can you figure out what pin number it is trying to use?
> >
> > Thanks,
> >
> > Mark
> >
> > P.S. Feel free to finish the driver yourself if you have time. This
> > sort of thing is way easier if you have the hardware. The
> > hardware itself should be very similar to aplgpio(4). It's just
> > that the registers moved around a bit and there is a single ACPI
> > device for all the pin "communities" instead of the model of
> > separate ACPI devices for each community that aplgpio(4) uses.
> >
>
> Election day surprise! Touchpad now works on my 400 Series laptop INT34BB.
>
> Please test on Sunrisepoint/100 Series INT344B as I do not have that hardware.
>
> The Cannonlake INT34BB controller is numbered as if there are 32 GPIO pins
> per group. The real pins are packed together and vary from 8 to 25 pins per
> group. In my case, GPIO 291 maps to pin 208, offset 27, bank 1, bar 2 (GPP_E).
>
> dmesg and vmstat -zi included. Interrupt count is after moving cursor to
> xterm.
Thanks James,
I'll have a closer look later, but the way forward is probably to
commit this with just the Cannon Lake support and add the other
generations later. I can make the necessary changes to that later
myself.
> Index: arch/amd64/conf/GENERIC
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
> retrieving revision 1.494
> diff -u -p -u -r1.494 GENERIC
> --- arch/amd64/conf/GENERIC 27 Oct 2020 02:39:07 -0000 1.494
> +++ arch/amd64/conf/GENERIC 4 Nov 2020 02:03:06 -0000
> @@ -66,6 +66,7 @@ aplgpio* at acpi?
> bytgpio* at acpi?
> chvgpio* at acpi?
> glkgpio* at acpi?
> +pchgpio* at acpi?
> sdhc* at acpi?
> acpicbkbd* at acpi?
> acpials* at acpi?
> Index: dev/acpi/files.acpi
> ===================================================================
> RCS file: /cvs/src/sys/dev/acpi/files.acpi,v
> retrieving revision 1.58
> diff -u -p -u -r1.58 files.acpi
> --- dev/acpi/files.acpi 27 Oct 2020 02:39:07 -0000 1.58
> +++ dev/acpi/files.acpi 4 Nov 2020 02:03:07 -0000
> @@ -151,6 +151,11 @@ device glkgpio
> attach glkgpio at acpi
> file dev/acpi/glkgpio.c glkgpio
>
> +# Intel PCH GPIO
> +device pchgpio
> +attach pchgpio at acpi
> +file dev/acpi/pchgpio.c pchgpio
> +
> # "Intel" Dollar Cove TI PMIC
> device tipmic
> attach tipmic at i2c
> Index: dev/acpi/pchgpio.c
> ===================================================================
> RCS file: dev/acpi/pchgpio.c
> diff -N dev/acpi/pchgpio.c
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ dev/acpi/pchgpio.c 4 Nov 2020 02:03:07 -0000
> @@ -0,0 +1,415 @@
> +/* $OpenBSD$ */
> +/*
> + * Copyright (c) 2020 Mark Kettenis
> + * Copyright (c) 2020 James Hastings
> + *
> + * Permission to use, copy, modify, and distribute this software for any
> + * purpose with or without fee is hereby granted, provided that the above
> + * copyright notice and this permission notice appear in all copies.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> + */
> +
> +#include <sys/param.h>
> +#include <sys/malloc.h>
> +#include <sys/systm.h>
> +
> +#include <dev/acpi/acpireg.h>
> +#include <dev/acpi/acpivar.h>
> +#include <dev/acpi/acpidev.h>
> +#include <dev/acpi/amltypes.h>
> +#include <dev/acpi/dsdt.h>
> +
> +#define PCHGPIO_MAXCOM 4
> +
> +#define PCHGPIO_CONF_TXSTATE 0x00000001
> +#define PCHGPIO_CONF_RXSTATE 0x00000002
> +#define PCHGPIO_CONF_RXINV 0x00800000
> +#define PCHGPIO_CONF_RXEV_EDGE 0x02000000
> +#define PCHGPIO_CONF_RXEV_ZERO 0x04000000
> +#define PCHGPIO_CONF_RXEV_MASK 0x06000000
> +
> +#define PCHGPIO_PADBAR 0x00c
> +
> +struct pchgpio_group {
> + uint8_t bar;
> + uint8_t bank;
> + uint16_t base;
> + uint16_t limit;
> + uint16_t offset;
> + int16_t gpiobase;
> +};
> +
> +struct pchgpio_device {
> + uint16_t pad_own;
> + uint16_t pad_size;
> + uint16_t padcfglock;
> + uint16_t hostsw_own;
> + uint16_t gpi_is;
> + uint16_t gpi_ie;
> + struct pchgpio_group *groups;
> + int ngroups;
> + int npins;
> +};
> +
> +struct pchgpio_match {
> + const char *hid;
> + struct pchgpio_device *device;
> +};
> +
> +struct pchgpio_intrhand {
> + int (*ih_func)(void *);
> + void *ih_arg;
> +};
> +
> +struct pchgpio_softc {
> + struct device sc_dev;
> + struct acpi_softc *sc_acpi;
> + struct aml_node *sc_node;
> +
> + bus_space_tag_t sc_memt[PCHGPIO_MAXCOM];
> + bus_space_handle_t sc_memh[PCHGPIO_MAXCOM];
> + void *sc_ih;
> + int sc_naddr;
> +
> + struct pchgpio_device *sc_device;
> + uint16_t sc_padbar[PCHGPIO_MAXCOM];
> + int sc_padsize;
> +
> + int sc_npins;
> + struct pchgpio_intrhand *sc_pin_ih;
> +
> + struct acpi_gpio sc_gpio;
> +};
> +
> +int pchgpio_match(struct device *, void *, void *);
> +void pchgpio_attach(struct device *, struct device *, void *);
> +
> +struct cfattach pchgpio_ca = {
> + sizeof(struct pchgpio_softc), pchgpio_match, pchgpio_attach
> +};
> +
> +struct cfdriver pchgpio_cd = {
> + NULL, "pchgpio", DV_DULL
> +};
> +
> +const char *pchgpio_hids[] = {
> + "INT344B",
> + "INT34BB",
> + NULL
> +};
> +
> +struct pchgpio_group spt_lp_groups[] =
> +{
> + /* Community 0 */
> + { 0, 0, 0, 23, 0, 0 }, /* GPP_A */
> + { 0, 1, 24, 47, 24, 24 }, /* GPP_B */
> +
> + /* Community 1 */
> + { 1, 0, 48, 71, 0, 48 }, /* GPP_C */
> + { 1, 1, 72, 95, 24, 72 }, /* GPP_D */
> + { 1, 2, 96, 119, 48, 96 }, /* GPP_E */
> +
> + /* Community 3 */
> + { 2, 0, 120, 143, 0, 120 }, /* GPP_F */
> + { 2, 1, 144, 151, 24, 144 }, /* GPP_G */
> +};
> +
> +struct pchgpio_device spt_lp_device =
> +{
> + .pad_own = 0x20,
> + .pad_size = 8,
> + .padcfglock = 0x100,
> + .hostsw_own = 0x0d0,
> + .gpi_is = 0x100,
> + .gpi_ie = 0x120,
> + .groups = spt_lp_groups,
> + .ngroups = nitems(spt_lp_groups),
> + .npins = 168,
> +};
> +
> +struct pchgpio_group cnl_lp_groups[] =
> +{
> + /* Community 0 */
> + { 0, 0, 0, 24, 0, 0 }, /* GPP_A */
> + { 0, 1, 25, 50, 25, 32 }, /* GPP_B */
> + { 0, 2, 51, 58, 51, 64 }, /* GPP_G */
> +
> + /* Community 1 */
> + { 1, 0, 68, 92, 0, 96 }, /* GPP_D */
> + { 1, 1, 93, 116, 24, 128 }, /* GPP_F */
> + { 1, 2, 117, 140, 48, 160 }, /* GPP_H */
> +
> + /* Community 4 */
> + { 2, 0, 181, 204, 0, 256 }, /* GPP_C */
> + { 2, 1, 205, 228, 24, 288 }, /* GPP_E */
> +};
> +
> +struct pchgpio_device cnl_lp_device =
> +{
> + .pad_own = 0x20,
> + .pad_size = 16,
> + .padcfglock = 0x80,
> + .hostsw_own = 0xb0,
> + .gpi_is = 0x100,
> + .gpi_ie = 0x120,
> + .groups = cnl_lp_groups,
> + .ngroups = nitems(cnl_lp_groups),
> + .npins = 320,
> +};
> +
> +struct pchgpio_match pchgpio_devices[] = {
> + { "INT344B", &spt_lp_device },
> + { "INT34BB", &cnl_lp_device },
> +};
> +
> +int pchgpio_read_pin(void *, int);
> +void pchgpio_write_pin(void *, int, int);
> +void pchgpio_intr_establish(void *, int, int, int (*)(), void *);
> +int pchgpio_intr(void *);
> +
> +int
> +pchgpio_match(struct device *parent, void *match, void *aux)
> +{
> + struct acpi_attach_args *aaa = aux;
> + struct cfdata *cf = match;
> +
> + return acpi_matchhids(aaa, pchgpio_hids, cf->cf_driver->cd_name);
> +}
> +
> +void
> +pchgpio_attach(struct device *parent, struct device *self, void *aux)
> +{
> + struct pchgpio_softc *sc = (struct pchgpio_softc *)self;
> + struct acpi_attach_args *aaa = aux;
> + int i;
> +
> + sc->sc_acpi = (struct acpi_softc *)parent;
> + sc->sc_node = aaa->aaa_node;
> + printf(" %s", sc->sc_node->name);
> +
> + if (aaa->aaa_naddr < 1) {
> + printf(": no registers\n");
> + return;
> + }
> +
> + if (aaa->aaa_nirq < 1) {
> + printf(": no interrupt\n");
> + return;
> + }
> +
> + printf(" addr");
> +
> + for (i = 0; i < aaa->aaa_naddr; i++) {
> + printf(" 0x%llx/0x%llx", aaa->aaa_addr[i], aaa->aaa_size[i]);
> +
> + sc->sc_memt[i] = aaa->aaa_bst[i];
> + if (bus_space_map(sc->sc_memt[i], aaa->aaa_addr[i],
> + aaa->aaa_size[i], 0, &sc->sc_memh[i])) {
> + printf(": can't map registers\n");
> + goto unmap;
> + }
> +
> + sc->sc_padbar[i] = bus_space_read_4(sc->sc_memt[i],
> + sc->sc_memh[i], PCHGPIO_PADBAR);
> + sc->sc_naddr++;
> + }
> +
> + printf(" irq %d", aaa->aaa_irq[0]);
> +
> + for (i = 0; i < nitems(pchgpio_devices); i++) {
> + if (strcmp(pchgpio_devices[i].hid, aaa->aaa_dev) == 0) {
> + sc->sc_device = pchgpio_devices[i].device;
> + break;
> + }
> + }
> + KASSERT(sc->sc_device);
> +
> + sc->sc_padsize = sc->sc_device->pad_size;
> + sc->sc_npins = sc->sc_device->npins;
> + sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih),
> + M_DEVBUF, M_WAITOK | M_ZERO);
> +
> + sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0],
> + IPL_BIO, pchgpio_intr, sc, sc->sc_dev.dv_xname);
> + if (sc->sc_ih == NULL) {
> + printf(": can't establish interrupt\n");
> + goto unmap;
> + }
> +
> + sc->sc_gpio.cookie = sc;
> + sc->sc_gpio.read_pin = pchgpio_read_pin;
> + sc->sc_gpio.write_pin = pchgpio_write_pin;
> + sc->sc_gpio.intr_establish = pchgpio_intr_establish;
> + sc->sc_node->gpio = &sc->sc_gpio;
> +
> +#if 0
> + /* Mask and clear all interrupts. */
> + uint8_t bank, bar;
> + for (i = 0; i < sc->sc_device->ngroups; i++) {
> + bank = sc->sc_device->groups[i].bank;
> + bar = sc->sc_device->groups[i].bar;
> +
> + bus_space_write_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_device->gpi_ie + bank * 4, 0x00000000);
> + bus_space_write_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_device->gpi_is + bank * 4, 0xffffffff);
> + }
> +#endif
> +
> + printf(", %d pins\n", sc->sc_npins);
> +
> + acpi_register_gpio(sc->sc_acpi, sc->sc_node);
> + return;
> +
> +unmap:
> + free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih));
> + for (i = 0; i < sc->sc_naddr; i++)
> + bus_space_unmap(sc->sc_memt[i], sc->sc_memh[i],
> + aaa->aaa_size[i]);
> +}
> +
> +struct pchgpio_group *
> +pchgpio_find_group(struct pchgpio_softc *sc, int pin)
> +{
> + int i, npads;
> +
> + for (i = 0; i < sc->sc_device->ngroups; i++) {
> + npads = 1 + sc->sc_device->groups[i].limit -
> + sc->sc_device->groups[i].base;
> +
> + if (pin >= sc->sc_device->groups[i].gpiobase &&
> + pin < sc->sc_device->groups[i].gpiobase + npads)
> + return &sc->sc_device->groups[i];
> + }
> + return NULL;
> +}
> +
> +int
> +pchgpio_read_pin(void *cookie, int pin)
> +{
> + struct pchgpio_softc *sc = cookie;
> + struct pchgpio_group *group;
> + uint32_t reg;
> + uint16_t offset;
> + uint8_t bar;
> +
> + group = pchgpio_find_group(sc, pin);
> + offset = group->offset + (pin - group->gpiobase);
> + bar = group->bar;
> +
> + reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_padbar[bar] + offset * sc->sc_padsize);
> +
> + return !!(reg & PCHGPIO_CONF_RXSTATE);
> +}
> +
> +void
> +pchgpio_write_pin(void *cookie, int pin, int value)
> +{
> + struct pchgpio_softc *sc = cookie;
> + struct pchgpio_group *group;
> + uint32_t reg;
> + uint16_t offset;
> + uint8_t bar;
> +
> + group = pchgpio_find_group(sc, pin);
> + offset = group->offset + (pin - group->gpiobase);
> + bar = group->bar;
> +
> + reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_padbar[bar] + offset * sc->sc_padsize);
> + if (value)
> + reg |= PCHGPIO_CONF_TXSTATE;
> + else
> + reg &= ~PCHGPIO_CONF_TXSTATE;
> + bus_space_write_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_padbar[bar] + offset * sc->sc_padsize, reg);
> +}
> +
> +void
> +pchgpio_intr_establish(void *cookie, int pin, int flags,
> + int (*func)(void *), void *arg)
> +{
> + struct pchgpio_softc *sc = cookie;
> + struct pchgpio_group *group;
> + uint32_t reg;
> + uint16_t offset;
> + uint8_t bank, bar;
> +
> + KASSERT(pin >= 0 && pin < sc->sc_npins);
> +
> + if ((group = pchgpio_find_group(sc, pin)) == NULL)
> + return;
> +
> + offset = group->offset + (pin - group->gpiobase);
> + bar = group->bar;
> + bank = group->bank;
> +
> + sc->sc_pin_ih[pin].ih_func = func;
> + sc->sc_pin_ih[pin].ih_arg = arg;
> +
> + reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_padbar[bar] + offset * sc->sc_padsize);
> + reg &= ~(PCHGPIO_CONF_RXEV_MASK | PCHGPIO_CONF_RXINV);
> + if ((flags & LR_GPIO_MODE) == 1)
> + reg |= PCHGPIO_CONF_RXEV_EDGE;
> + if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO)
> + reg |= PCHGPIO_CONF_RXINV;
> + if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH)
> + reg |= PCHGPIO_CONF_RXEV_EDGE | PCHGPIO_CONF_RXEV_ZERO;
> + bus_space_write_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_padbar[bar] + offset * sc->sc_padsize, reg);
> +
> + reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_device->gpi_ie + bank * 4);
> + reg |= (1 << (pin - group->gpiobase));
> + bus_space_write_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_device->gpi_ie + bank * 4, reg);
> +}
> +
> +int
> +pchgpio_intr(void *arg)
> +{
> + struct pchgpio_softc *sc = arg;
> + uint32_t status, enable;
> + int gpiobase, group, bit, pin, handled = 0;
> + uint16_t base, limit;
> + uint16_t offset;
> + uint8_t bank, bar;
> +
> + for (group = 0; group < sc->sc_device->ngroups; group++) {
> + bar = sc->sc_device->groups[group].bar;
> + bank = sc->sc_device->groups[group].bank;
> + base = sc->sc_device->groups[group].base;
> + limit = sc->sc_device->groups[group].limit;
> + offset = sc->sc_device->groups[group].offset;
> + gpiobase = sc->sc_device->groups[group].gpiobase;
> +
> + status = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_device->gpi_is + bank * 4);
> + bus_space_write_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_device->gpi_is + bank * 4, status);
> + enable = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
> + sc->sc_device->gpi_ie + bank * 4);
> + status &= enable;
> + if (status == 0)
> + continue;
> +
> + for (bit = 0; bit <= (limit - base); bit++) {
> + pin = gpiobase + bit;
> + if (status & (1 << bit) &&
> + sc->sc_pin_ih[pin].ih_func)
> +
> sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg);
> + handled = 1;
> + }
> + }
> +
> + return handled;
> +}
>
>
> dmesg:
> OpenBSD 6.8-current (GENERIC.MP) #37: Tue Nov 3 20:41:35 EST 2020
> [email protected]:/usr/src/sys/arch/amd64/compile/GENERIC.MP
> real mem = 8252678144 (7870MB)
> avail mem = 7987212288 (7617MB)
> random: good seed from bootblocks
> mpath0 at root
> scsibus0 at mpath0: 256 targets
> mainbus0 at root
> bios0 at mainbus0: SMBIOS rev. 3.2 @ 0x8d901000 (69 entries)
> bios0: vendor Insyde version "F.03" date 08/01/2019
> bios0: HP HP Pavilion x360 Convertible 14m-dh1xxx
> acpi0 at bios0: ACPI 5.1
> acpi0: sleep states S0 S3 S4 S5
> acpi0: tables DSDT FACP UEFI SSDT SSDT SSDT SSDT SSDT TPM2 SSDT SSDT MSDM
> LPIT WSMT SSDT SSDT DBGP DBG2 SSDT SSDT NHLT HPET APIC MCFG SSDT DMAR SSDT
> SSDT SSDT UEFI UEFI FPDT BGRT
> acpi0: wakeup devices XHC_(S3) XDCI(S4) HDAS(S4) RP01(S4) PXSX(S4) RP02(S4)
> PXSX(S4) RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) PEGA(S4)
> RP06(S4) PXSX(S4) [...]
> acpitimer0 at acpi0: 3579545 Hz, 24 bits
> acpihpet0 at acpi0: 23999999 Hz
> acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
> cpu0 at mainbus0: apid 0 (boot processor)
> cpu0: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3890.80 MHz, 06-8e-0c
> cpu0:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu0: 256KB 64b/line 8-way L2 cache
> cpu0: smt 0, core 0, package 0
> mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
> cpu0: apic clock running at 24MHz
> cpu0: mwait min=64, max=64, C-substates=0.2.1.2.4.1.1.1, IBE
> cpu1 at mainbus0: apid 2 (application processor)
> cpu1: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3890.94 MHz, 06-8e-0c
> cpu1:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu1: 256KB 64b/line 8-way L2 cache
> cpu1: smt 0, core 1, package 0
> cpu2 at mainbus0: apid 4 (application processor)
> cpu2: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3890.94 MHz, 06-8e-0c
> cpu2:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu2: 256KB 64b/line 8-way L2 cache
> cpu2: smt 0, core 2, package 0
> cpu3 at mainbus0: apid 6 (application processor)
> cpu3: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3700.33 MHz, 06-8e-0c
> cpu3:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu3: 256KB 64b/line 8-way L2 cache
> cpu3: smt 0, core 3, package 0
> cpu4 at mainbus0: apid 1 (application processor)
> cpu4: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3656.63 MHz, 06-8e-0c
> cpu4:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu4: 256KB 64b/line 8-way L2 cache
> cpu4: smt 1, core 0, package 0
> cpu5 at mainbus0: apid 3 (application processor)
> cpu5: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3624.42 MHz, 06-8e-0c
> cpu5:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu5: 256KB 64b/line 8-way L2 cache
> cpu5: smt 1, core 1, package 0
> cpu6 at mainbus0: apid 5 (application processor)
> cpu6: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3603.47 MHz, 06-8e-0c
> cpu6:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu6: 256KB 64b/line 8-way L2 cache
> cpu6: smt 1, core 2, package 0
> cpu7 at mainbus0: apid 7 (application processor)
> cpu7: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz, 3579.89 MHz, 06-8e-0c
> cpu7:
> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
> cpu7: 256KB 64b/line 8-way L2 cache
> cpu7: smt 1, core 3, package 0
> ioapic0 at mainbus0: apid 2 pa 0xfec00000, version 20, 120 pins
> acpimcfg0 at acpi0
> acpimcfg0: addr 0xe0000000, bus 0-255
> acpiprt0 at acpi0: bus 0 (PCI0)
> acpiprt1 at acpi0: bus -1 (RP01)
> acpiprt2 at acpi0: bus -1 (RP02)
> acpiprt3 at acpi0: bus -1 (RP03)
> acpiprt4 at acpi0: bus -1 (RP04)
> acpiprt5 at acpi0: bus -1 (RP05)
> acpiprt6 at acpi0: bus -1 (RP06)
> acpiprt7 at acpi0: bus -1 (RP07)
> acpiprt8 at acpi0: bus -1 (RP08)
> acpiprt9 at acpi0: bus 1 (RP09)
> acpiprt10 at acpi0: bus 6 (RP10)
> acpiprt11 at acpi0: bus -1 (RP11)
> acpiprt12 at acpi0: bus -1 (RP12)
> acpiprt13 at acpi0: bus 11 (RP13)
> acpiprt14 at acpi0: bus -1 (RP14)
> acpiprt15 at acpi0: bus 16 (RP15)
> acpiprt16 at acpi0: bus -1 (RP16)
> acpiprt17 at acpi0: bus -1 (RP17)
> acpiprt18 at acpi0: bus -1 (RP18)
> acpiprt19 at acpi0: bus -1 (RP19)
> acpiprt20 at acpi0: bus -1 (RP20)
> acpiprt21 at acpi0: bus -1 (RP21)
> acpiprt22 at acpi0: bus -1 (RP22)
> acpiprt23 at acpi0: bus -1 (RP23)
> acpiprt24 at acpi0: bus -1 (RP24)
> acpiec0 at acpi0
> acpiec0: Not running on HW-Reduced ACPI type 8
> acpiec0: invalid resource #3 type 134
> acpipci0 at acpi0 PCI0: 0x00000000 0x00000011 0x00000001
> acpiac0 at acpi0: AC unit offline
> acpibat0 at acpi0: BAT0 model "HT03041XL" type LION
> "INT33D2" at acpi0 not configured
> "INT33D3" at acpi0 not configured
> "INT3403" at acpi0 not configured
> "INT3403" at acpi0 not configured
> pchgpio0 at acpi0 GPI0 addr 0xfd6e0000/0x10000 0xfd6d0000/0x10000
> 0xfd6a0000/0x10000 irq 14, 320 pins
> "SYNA328B" at acpi0 not configured
> "ELAN2514" at acpi0 not configured
> "ACPI000E" at acpi0 not configured
> "PNP0C14" at acpi0 not configured
> "INT0E0C" at acpi0 not configured
> "PNP0C14" at acpi0 not configured
> "PNP0C14" at acpi0 not configured
> "INT33A1" at acpi0 not configured
> acpihid0 at acpi0: HIDD, 5 button array
> acpibtn0 at acpi0: LID0
> acpibtn1 at acpi0: PWRB
> "PNP0C14" at acpi0 not configured
> "HPQ6001" at acpi0 not configured
> "HPQ6007" at acpi0 not configured
> "INT3400" at acpi0 not configured
> "MSFT0101" at acpi0 not configured
> "PNP0C14" at acpi0 not configured
> "HPIC0003" at acpi0 not configured
> acpipwrres0 at acpi0: USBC, resource for XDCI
> acpipwrres1 at acpi0: PCRP, resource for RP05
> acpipwrres2 at acpi0: V0PR
> acpipwrres3 at acpi0: V1PR
> acpipwrres4 at acpi0: V2PR
> acpipwrres5 at acpi0: WRST
> acpicpu0 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpicpu1 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpicpu2 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpicpu3 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpicpu4 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpicpu5 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpicpu6 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpicpu7 at acpi0: C3(200@1034 mwait.1@0x60), C2(200@151 mwait.1@0x33),
> C1(1000@1 mwait.1), PSS
> acpitz0 at acpi0: critical temperature is 120 degC
> acpitz1 at acpi0: critical temperature is 120 degC
> acpipwrres6 at acpi0: PIN_
> acpidock0 at acpi0: DOCK not docked (0)
> acpivideo0 at acpi0: GFX0
> acpivout0 at acpivideo0: DD02
> acpivout1 at acpivideo0: DD1F
> cpu0: Enhanced SpeedStep 3890 MHz: speeds: 2101, 2100, 2000, 1900, 1700,
> 1600, 1500, 1400, 1200, 1100, 1000, 800, 700, 600, 500, 400 MHz
> pci0 at mainbus0 bus 0
> pchb0 at pci0 dev 0 function 0 "Intel Core 10G Host" rev 0x0c
> inteldrm0 at pci0 dev 2 function 0 "Intel UHD Graphics" rev 0x02
> drm0 at inteldrm0
> inteldrm0: msi, COFFEELAKE, gen 9
> "Intel Core 6G Thermal" rev 0x0c at pci0 dev 4 function 0 not configured
> "Intel Core GMM" rev 0x00 at pci0 dev 8 function 0 not configured
> pchtemp0 at pci0 dev 18 function 0 "Intel 400 Series Thermal" rev 0x00
> "Intel 400 Series ISH" rev 0x00 at pci0 dev 19 function 0 not configured
> xhci0 at pci0 dev 20 function 0 "Intel 400 Series xHCI" rev 0x00: msi, xHCI
> 1.10
> usb0 at xhci0: USB revision 3.0
> uhub0 at usb0 configuration 1 interface 0 "Intel xHCI root hub" rev 3.00/1.00
> addr 1
> "Intel 400 Series Shared SRAM" rev 0x00 at pci0 dev 20 function 2 not
> configured
> sdhc0 at pci0 dev 20 function 5 "Intel 400 Series SDXC" rev 0x00: apic 2 int
> 19
> sdhc0: SDHC 3.0, 200 MHz base clock
> sdmmc0 at sdhc0: 4-bit, sd high-speed, mmc high-speed, ddr52, dma
> dwiic0 at pci0 dev 21 function 0 "Intel 400 Series I2C" rev 0x00: apic 2 int
> 16
> iic0 at dwiic0
> ihidev0 at iic0 addr 0x2c gpio 291, vendor 0x6cb product 0xcd50, SYNA328B
> ihidev0: 31 report ids
> imt0 at ihidev0: clickpad, 5 contacts
> wsmouse0 at imt0 mux 0
> ims0 at ihidev0 reportid 2: 2 buttons
> wsmouse1 at ims0 mux 0
> hid at ihidev0 reportid 6 not configured
> hid at ihidev0 reportid 7 not configured
> hid at ihidev0 reportid 9 not configured
> hid at ihidev0 reportid 10 not configured
> hid at ihidev0 reportid 11 not configured
> hid at ihidev0 reportid 12 not configured
> hid at ihidev0 reportid 13 not configured
> hid at ihidev0 reportid 14 not configured
> hid at ihidev0 reportid 15 not configured
> hid at ihidev0 reportid 29 not configured
> hid at ihidev0 reportid 31 not configured
> dwiic1 at pci0 dev 21 function 1 "Intel 400 Series I2C" rev 0x00: apic 2 int
> 17
> iic1 at dwiic1
> ihidev1 at iic1 addr 0x10 gpio 295, vendor 0x4f3 product 0x23dd, ELAN2514
> ihidev1: 23 report ids
> ims1 at ihidev1 reportid 1: 1 button, tip
> wsmouse2 at ims1 mux 0
> hid at ihidev1 reportid 2 not configured
> hid at ihidev1 reportid 3 not configured
> hid at ihidev1 reportid 4 not configured
> hid at ihidev1 reportid 6 not configured
> ims2 at ihidev1 reportid 7: 3 buttons, tip, barrel, eraser
> wsmouse3 at ims2 mux 0
> hid at ihidev1 reportid 10 not configured
> hid at ihidev1 reportid 14 not configured
> hid at ihidev1 reportid 23 not configured
> "Intel 400 Series MEI" rev 0x00 at pci0 dev 22 function 0 not configured
> pciide0 at pci0 dev 23 function 0 "Intel 82801HBM RAID" rev 0x00: DMA,
> channel 0 wired to native-PCI, channel 1 wired to native-PCI
> pciide0: using apic 2 int 16 for native-PCI interrupt
> ppb0 at pci0 dev 29 function 0 "Intel 400 Series PCIE" rev 0xf0: msi
> pci1 at ppb0 bus 1
> ppb1 at pci0 dev 29 function 1 "Intel 400 Series PCIE" rev 0xf0: msi
> pci2 at ppb1 bus 6
> "Realtek 8821CE" rev 0x00 at pci2 dev 0 function 0 not configured
> ppb2 at pci0 dev 29 function 4 "Intel 400 Series PCIE" rev 0xf0: msi
> pci3 at ppb2 bus 11
> nvme0 at pci3 dev 0 function 0 vendor "Intel", unknown product 0x0975 rev
> 0x03: msix, NVMe 1.3
> nvme0: INTEL HBRPEKNX0101AH, firmware HPS1, serial
> scsibus1 at nvme0: 2 targets, initiator 0
> sd0 at scsibus1 targ 1 lun 0: <NVMe, INTEL HBRPEKNX01, HPS1>
> sd0: 244198MB, 512 bytes/sector, 500118192 sectors
> ppb3 at pci0 dev 29 function 6 "Intel 400 Series PCIE" rev 0xf0: msi
> pci4 at ppb3 bus 16
> nvme1 at pci4 dev 0 function 0 vendor "Intel", unknown product 0x0975 rev
> 0x00: msix, NVMe 1.1
> nvme1: INTEL HBRPEKNX0101AHO, firmware HPS2, serial
> scsibus2 at nvme1: 2 targets, initiator 0
> sd1 at scsibus2 targ 1 lun 0: <NVMe, INTEL HBRPEKNX01, HPS2>
> sd1: 13736MB, 512 bytes/sector, 28131328 sectors
> pcib0 at pci0 dev 31 function 0 "Intel 400 Series LPC" rev 0x00
> azalia0 at pci0 dev 31 function 3 "Intel 400 Series HD Audio" rev 0x00: msi
> azalia0: codecs: Realtek ALC295, Intel/0x280b, using Realtek ALC295
> audio0 at azalia0
> ichiic0 at pci0 dev 31 function 4 "Intel 400 Series SMBus" rev 0x00: apic 2
> int 16
> iic2 at ichiic0
> spdmem0 at iic2 addr 0x50: 8GB DDR4 SDRAM PC4-21300 SO-DIMM
> "Intel 400 Series SPI" rev 0x00 at pci0 dev 31 function 5 not configured
> isa0 at pcib0
> isadma0 at isa0
> pckbc0 at isa0 port 0x60/5 irq 1 irq 12
> pckbd0 at pckbc0 (kbd slot)
> wskbd0 at pckbd0: console keyboard
> pms0 at pckbc0 (aux slot)
> wsmouse4 at pms0 mux 0
> pms0: Synaptics clickpad, firmware 10.16, 0x1e2a1 0x840300 0x365040 0xf00623
> 0x12e800
> pcppi0 at isa0 port 0x61
> spkr0 at pcppi0
> vmm0 at mainbus0: VMX/EPT
> efifb at mainbus0 not configured
> umass0 at uhub0 port 2 configuration 1 interface 0 "SanDisk Cruzer Glide" rev
> 2.00/1.00 addr 2
> umass0: using SCSI over Bulk-Only
> scsibus3 at umass0: 2 targets, initiator 0
> sd2 at scsibus3 targ 1 lun 0: <SanDisk, Cruzer Glide, 1.00> removable
> sd2: 15060MB, 512 bytes/sector, 30842880 sectors
> uvideo0 at uhub0 port 4 configuration 1 interface 0 "DHQYLA19ICME8I HP Wide
> Vision HD Camera" rev 2.01/0.04 addr 3
> video0 at uvideo0
> ugen0 at uhub0 port 5 "Synaptics product 0x00cb" rev 2.00/1.64 addr 4
> ugen1 at uhub0 port 10 "Realtek Bluetooth Radio" rev 1.10/1.10 addr 5
> vscsi0 at root
> scsibus4 at vscsi0: 256 targets
> softraid0 at root
> scsibus5 at softraid0: 256 targets
> root on sd2a (c451627de5fb62d6.a) swap on sd2b dump on sd2b
> inteldrm0: 1920x1080, 32bpp
> wsdisplay0 at inteldrm0 mux 1: console (std, vt100 emulation), using wskbd0
> wsdisplay0: screen 1-5 added (std, vt100 emulation)
>
> vmstat -zi:
> interrupt total rate
> irq0/clock 180234 790
> irq0/ipi 3510 15
> irq96/pchgpio0 279 1
> irq97/acpi0 7 0
> irq144/inteldrm0 572 2
> irq98/xhci0 101025 443
> irq99/sdhc0 0 0
> irq108/dwiic0 22 0
> irq101/dwiic1 16 0
> irq108/pciide0 22 0
> irq100/ppb0 0 0
> irq103/ppb1 0 0
> irq104/ppb2 0 0
> irq105/nvme0 112 0
> irq106/ppb3 0 0
> irq107/nvme1 13 0
> irq176/azalia0 1 0
> irq108/ichiic0 0 0
> irq145/pckbc0 165 0
> irq146/pckbc0 116 0
> Total 286094 1254
>
>
