Intel calls it "IA32_TSC_ADJUST". Is "MSR_TSC_ADJUST" fine or should it be "MSR_IA32_TSC_ADJUST"?
We have a feature flag for this one already, SEFF0EBX_TSC_ADJUST. Index: specialreg.h =================================================================== RCS file: /cvs/src/sys/arch/amd64/include/specialreg.h,v retrieving revision 1.89 diff -u -p -r1.89 specialreg.h --- specialreg.h 29 Mar 2021 12:39:02 -0000 1.89 +++ specialreg.h 6 Apr 2021 00:31:58 -0000 @@ -352,6 +352,7 @@ #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ #define MSR_TEST_CTL 0x033 #define MSR_IA32_FEATURE_CONTROL 0x03a +#define MSR_TSC_ADJUST 0x03b #define MSR_SPEC_CTRL 0x048 /* Speculation Control IBRS / STIBP */ #define SPEC_CTRL_IBRS (1ULL << 0) #define SPEC_CTRL_STIBP (1ULL << 1)
