On Thu, Jun 10, 2021 at 03:19:43PM +1000, Jonathan Gray wrote:
> Ilya Voronin sent a diff to misc to limit MSR_INT_PEN_MSG use to
> < AMD family 17h prompted by a problem with an AWS t3a instance.
>
> https://marc.info/?l=openbsd-misc&m=162120066715633&w=2
>
> Digging some more the 16h bkdgs have it as RAZ/non-functional as well.
> Bits are documented in 15h.
>
> BKDG for AMD Family 16h Models 00h-0Fh Processors
> MSRC001_0055 Interrupt Pending
> 63:0 RAZ.
>
> BKDG for AMD Family 16h Models 30h-3Fh Processors
> MSRC001_0055 Interrupt Pending
> 63:0 RAZ
>
> PPR for AMD Family 17h Model 71h B0
> MSRC001_0055 [Reserved.] (Core::X86::Msr::IntPend)
> Read-only. Reset: Fixed,0000_0000_0000_0000h.
>
> Change the test to use extended family id while here.
>
I'd be ok with this if someone reported that it works on a bare metal EPYC,
since the fix here is for a virtualized environment (and we don't know what
AWS is doing here).
-ml
> Index: sys/arch/amd64/amd64/lapic.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/lapic.c,v
> retrieving revision 1.57
> diff -u -p -r1.57 lapic.c
> --- sys/arch/amd64/amd64/lapic.c 6 Sep 2020 20:50:00 -0000 1.57
> +++ sys/arch/amd64/amd64/lapic.c 19 May 2021 09:16:37 -0000
> @@ -299,8 +299,7 @@ lapic_set_lvt(void)
> * Family 0Fh Processors"
> * #32559 revision 3.00
> */
> - if ((cpu_id & 0x00000f00) == 0x00000f00 &&
> - (cpu_id & 0x0fff0000) >= 0x00040000) {
> + if (ci->ci_family >= 0xf && ci->ci_family < 0x16) {
> uint64_t msr;
>
> msr = rdmsr(MSR_INT_PEN_MSG);
> Index: sys/arch/i386/i386/lapic.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/i386/i386/lapic.c,v
> retrieving revision 1.47
> diff -u -p -r1.47 lapic.c
> --- sys/arch/i386/i386/lapic.c 30 Jul 2018 14:19:12 -0000 1.47
> +++ sys/arch/i386/i386/lapic.c 19 May 2021 09:19:41 -0000
> @@ -160,8 +160,7 @@ lapic_set_lvt(void)
> * Family 0Fh Processors"
> * #32559 revision 3.00
> */
> - if ((cpu_id & 0x00000f00) == 0x00000f00 &&
> - (cpu_id & 0x0fff0000) >= 0x00040000) {
> + if (ci->ci_family >= 0xf && ci->ci_family < 0x16) {
> uint64_t msr;
>
> msr = rdmsr(MSR_INT_PEN_MSG);
>
>
