On Thu, Mar 17, 2022 at 07:12:16AM +0000, Visa Hankala wrote: > On Wed, Mar 16, 2022 at 11:09:12PM +0100, Alexander Bluhm wrote: > > On Tue, Mar 15, 2022 at 09:15:34AM +0000, Visa Hankala wrote: > > > However, some DEC Alpha CPUs have their data caches divided into cache > > > banks to improve bandwidth. These cache banks are relatively > > > independent. The system maintains coherency, but bus contention can > > > delay propagation of cache updates. If the loads spanned different cache > > > banks, the second load could deliver data which is older than the > > > initial load's value. The data dependency barrier causes an interlock > > > with cache updating, ensuring causal ordering.) > > > > The code with the membar is copied from READ_ONCE() which is copied > > from Linux. The membar_datadep_consumer() has an #ifdef __alpha__ > > in it. It is only used for that case. I don't know whether we > > want to support such CPU. But if that is the case, we need the > > membar. > > Whether the membar is necessary or not depends on the use case. > READ_ONCE(), and SMR_PTR_GET(), have it built in so that loaded > pointers would work in the expected way in lockless contexts. This > is intentional, the membar has not been just copied there.
With that explanation OK bluhm@ to remove the membar.
