So I did "objdump -t bsd | fgrep 'O .data' | sort -k5r" on arm64.
Oh my.
The diff below constifies a myriad of pin, clock, etc. tables.
This is all very mechanical. An arm64 GENERIC.MP kernel still
builds and boots with this.
OK?
M sys/dev/fdt/amlclock.c
M sys/dev/fdt/amlpinctrl.c
M sys/dev/fdt/axppmic.c
M sys/dev/fdt/bd718x7.c
M sys/dev/fdt/hiclock.c
M sys/dev/fdt/hitemp.c
M sys/dev/fdt/imxccm.c
M sys/dev/fdt/imxccm_clocks.h
M sys/dev/fdt/imxsrc.c
M sys/dev/fdt/mvpinctrl.c
M sys/dev/fdt/mvpinctrl_pins.h
M sys/dev/fdt/mvtemp.c
M sys/dev/fdt/rkclock.c
M sys/dev/fdt/rkpinctrl.c
M sys/dev/fdt/rkpmic.c
M sys/dev/fdt/rktemp.c
M sys/dev/fdt/sxiccmu.c
M sys/dev/fdt/sxiccmu_clocks.h
M sys/dev/fdt/sxipio.c
M sys/dev/fdt/sxipio_pins.h
M sys/dev/ic/imxiicvar.h
diff 1258159c23de129a92e61d9298f34d98b4b5be29
5f4acf3c29cf6656bcd1b87f26aad6cec8a72d21
blob - 9c26eec4407b5c58d3797d382d9978c395d6a100
blob + 6a8071eadb0fdadb2b4406090c1d07a02d2e5d87
--- sys/dev/fdt/amlclock.c
+++ sys/dev/fdt/amlclock.c
@@ -117,7 +117,7 @@ struct amlclock_gate {
uint8_t bit;
};
-struct amlclock_gate aml_g12a_gates[] = {
+const struct amlclock_gate aml_g12a_gates[] = {
[G12A_I2C] = { HHI_GCLK_MPEG0, 9 },
[G12A_SD_EMMC_A] = { HHI_GCLK_MPEG0, 24 },
[G12A_SD_EMMC_B] = { HHI_GCLK_MPEG0, 25 },
@@ -139,7 +139,7 @@ struct amlclock_softc {
int sc_node;
uint32_t sc_g12b;
- struct amlclock_gate *sc_gates;
+ const struct amlclock_gate *sc_gates;
int sc_ngates;
struct clock_device sc_cd;
blob - d03c0146d6d73d51730813125ac5259b4b20c371
blob + 4508166611b9aac1c9fd4d04810cfdf2a282f504
--- sys/dev/fdt/amlpinctrl.c
+++ sys/dev/fdt/amlpinctrl.c
@@ -162,7 +162,7 @@ struct aml_pin_group {
const char *function;
};
-struct aml_gpio_bank aml_g12a_gpio_banks[] = {
+const struct aml_gpio_bank aml_g12a_gpio_banks[] = {
/* BOOT */
{ BOOT_0, 16,
PERIPHS_PIN_MUX_0 - PERIPHS_PIN_MUX_0, 0,
@@ -226,7 +226,7 @@ struct aml_gpio_bank aml_g12a_gpio_banks[] = {
{ }
};
-struct aml_pin_group aml_g12a_pin_groups[] = {
+const struct aml_pin_group aml_g12a_pin_groups[] = {
/* GPIOZ */
{ "i2c0_sda_z0", GPIOZ_0, 4, "i2c0" },
{ "i2c0_sck_z1", GPIOZ_1, 4, "i2c0" },
@@ -292,7 +292,7 @@ struct aml_pin_group aml_g12a_pin_groups[] = {
{ }
};
-struct aml_gpio_bank aml_g12a_ao_gpio_banks[] = {
+const struct aml_gpio_bank aml_g12a_ao_gpio_banks[] = {
/* GPIOAO */
{ GPIOAO_0, 12,
AO_RTI_PINMUX_0 - AO_RTI_PINMUX_0, 0,
@@ -316,7 +316,7 @@ struct aml_gpio_bank aml_g12a_ao_gpio_banks[] = {
{ }
};
-struct aml_pin_group aml_g12a_ao_pin_groups[] = {
+const struct aml_pin_group aml_g12a_ao_pin_groups[] = {
/* GPIOAO */
{ "uart_ao_a_tx", GPIOAO_0, 1, "uart_ao_a" },
{ "uart_ao_a_rx", GPIOAO_1, 1, "uart_ao_a" },
@@ -347,8 +347,8 @@ struct amlpinctrl_softc {
bus_space_handle_t sc_ds_ioh;
int sc_nobias;
- struct aml_gpio_bank *sc_gpio_banks;
- struct aml_pin_group *sc_pin_groups;
+ const struct aml_gpio_bank *sc_gpio_banks;
+ const struct aml_pin_group *sc_pin_groups;
struct gpio_controller sc_gc;
};
@@ -481,10 +481,10 @@ amlpinctrl_attach(struct device *parent, struct device
gpio_controller_register(&sc->sc_gc);
}
-struct aml_gpio_bank *
+const struct aml_gpio_bank *
amlpinctrl_lookup_bank(struct amlpinctrl_softc *sc, uint32_t pin)
{
- struct aml_gpio_bank *bank;
+ const struct aml_gpio_bank *bank;
for (bank = sc->sc_gpio_banks; bank->num_pins > 0; bank++) {
if (pin >= bank->first_pin &&
@@ -495,10 +495,10 @@ amlpinctrl_lookup_bank(struct amlpinctrl_softc *sc, ui
return NULL;
}
-struct aml_pin_group *
+const struct aml_pin_group *
amlpinctrl_lookup_group(struct amlpinctrl_softc *sc, const char *name)
{
- struct aml_pin_group *group;
+ const struct aml_pin_group *group;
for (group = sc->sc_pin_groups; group->name; group++) {
if (strcmp(name, group->name) == 0)
@@ -512,8 +512,8 @@ void
amlpinctrl_config_func(struct amlpinctrl_softc *sc, const char *name,
const char *function, int bias, int ds)
{
- struct aml_pin_group *group;
- struct aml_gpio_bank *bank;
+ const struct aml_pin_group *group;
+ const struct aml_gpio_bank *bank;
bus_addr_t off;
uint32_t pin;
uint32_t reg;
@@ -640,7 +640,7 @@ void
amlpinctrl_config_pin(void *cookie, uint32_t *cells, int config)
{
struct amlpinctrl_softc *sc = cookie;
- struct aml_gpio_bank *bank;
+ const struct aml_gpio_bank *bank;
bus_addr_t off;
uint32_t pin = cells[0];
uint32_t flags = cells[1];
@@ -678,7 +678,7 @@ int
amlpinctrl_get_pin(void *cookie, uint32_t *cells)
{
struct amlpinctrl_softc *sc = cookie;
- struct aml_gpio_bank *bank;
+ const struct aml_gpio_bank *bank;
bus_addr_t off;
uint32_t pin = cells[0];
uint32_t flags = cells[1];
@@ -707,7 +707,7 @@ void
amlpinctrl_set_pin(void *cookie, uint32_t *cells, int val)
{
struct amlpinctrl_softc *sc = cookie;
- struct aml_gpio_bank *bank;
+ const struct aml_gpio_bank *bank;
bus_addr_t off;
uint32_t pin = cells[0];
uint32_t flags = cells[1];
blob - 7e2b0c9994247f2c1e51eca6b28a30596d9bc844
blob + 449feaf311175a73b21f75c78dac33741015bcf5
--- sys/dev/fdt/axppmic.c
+++ sys/dev/fdt/axppmic.c
@@ -55,7 +55,7 @@ struct axppmic_regdata {
uint32_t base2, delta2;
};
-struct axppmic_regdata axp209_regdata[] = {
+const struct axppmic_regdata axp209_regdata[] = {
{ "dcdc2", 0x12, (1 << 4), (1 << 4), (0 << 4),
0x23, 0x3f, 700000, 25000 },
{ "dcdc3", 0x12, (1 << 1), (1 << 1), (0 << 1),
@@ -71,7 +71,7 @@ struct axppmic_regdata axp209_regdata[] = {
{ NULL }
};
-struct axppmic_regdata axp221_regdata[] = {
+const struct axppmic_regdata axp221_regdata[] = {
{ "dcdc1", 0x10, (1 << 1), (1 << 1), (0 << 1),
0x21, 0x1f, 1600000, 100000 },
{ "dcdc2", 0x10, (1 << 2), (1 << 2), (0 << 2),
@@ -112,7 +112,7 @@ struct axppmic_regdata axp221_regdata[] = {
{ NULL }
};
-struct axppmic_regdata axp803_regdata[] = {
+const struct axppmic_regdata axp803_regdata[] = {
{ "dcdc1", 0x10, (1 << 0), (1 << 0), (0 << 0),
0x20, 0x1f, 1600000, 100000 },
{ "dcdc2", 0x10, (1 << 1), (1 << 1), (0 << 1),
@@ -157,7 +157,7 @@ struct axppmic_regdata axp803_regdata[] = {
{ NULL }
};
-struct axppmic_regdata axp806_regdata[] = {
+const struct axppmic_regdata axp806_regdata[] = {
{ "dcdca", 0x10, (1 << 0), (1 << 0), (0 << 0),
0x12, 0x7f, 600000, 10000, 1120000, 20000 },
{ "dcdcb", 0x10, (1 << 1), (1 << 1), (0 << 1),
@@ -192,7 +192,7 @@ struct axppmic_regdata axp806_regdata[] = {
{ NULL }
};
-struct axppmic_regdata axp809_regdata[] = {
+const struct axppmic_regdata axp809_regdata[] = {
{ "dcdc1", 0x10, (1 << 1), (1 << 1), (0 << 1),
0x21, 0x1f, 1600000, 100000 },
{ "dcdc2", 0x10, (1 << 2), (1 << 2), (0 << 2),
@@ -239,7 +239,7 @@ struct axppmic_sensdata {
uint64_t base, delta;
};
-struct axppmic_sensdata axp209_sensdata[] = {
+const struct axppmic_sensdata axp209_sensdata[] = {
{ "ACIN", SENSOR_INDICATOR, 0x00, (1 << 7), (1 << 6) },
{ "VBUS", SENSOR_INDICATOR, 0x00, (1 << 5), (1 << 4) },
{ "ACIN", SENSOR_VOLTS_DC, 0x56, 0, 1700 },
@@ -251,21 +251,21 @@ struct axppmic_sensdata axp209_sensdata[] = {
{ NULL }
};
-struct axppmic_sensdata axp221_sensdata[] = {
+const struct axppmic_sensdata axp221_sensdata[] = {
{ "ACIN", SENSOR_INDICATOR, 0x00, (1 << 7), (1 << 6) },
{ "VBUS", SENSOR_INDICATOR, 0x00, (1 << 5), (1 << 4) },
{ "", SENSOR_TEMP, 0x56, 5450000, 105861 },
{ NULL }
};
-struct axppmic_sensdata axp803_sensdata[] = {
+const struct axppmic_sensdata axp803_sensdata[] = {
{ "ACIN", SENSOR_INDICATOR, 0x00, (1 << 7), (1 << 6) },
{ "VBUS", SENSOR_INDICATOR, 0x00, (1 << 5), (1 << 4) },
{ "", SENSOR_TEMP, 0x56, 5450000, 106250 },
{ NULL }
};
-struct axppmic_sensdata axp803_battery_sensdata[] = {
+const struct axppmic_sensdata axp803_battery_sensdata[] = {
{ "ACIN", SENSOR_INDICATOR, 0x00, (1 << 7), (1 << 6) },
{ "VBUS", SENSOR_INDICATOR, 0x00, (1 << 5), (1 << 4) },
{ "", SENSOR_TEMP, 0x56, 5450000, 106250 },
@@ -283,11 +283,11 @@ struct axppmic_sensdata axp803_battery_sensdata[] = {
struct axppmic_device {
const char *name;
const char *chip;
- struct axppmic_regdata *regdata;
- struct axppmic_sensdata *sensdata;
+ const struct axppmic_regdata *regdata;
+ const struct axppmic_sensdata *sensdata;
};
-struct axppmic_device axppmic_devices[] = {
+const struct axppmic_device axppmic_devices[] = {
{ "x-powers,axp152", "AXP152" },
{ "x-powers,axp209", "AXP209", axp209_regdata, axp209_sensdata },
{ "x-powers,axp221", "AXP221", axp221_regdata, axp221_sensdata },
@@ -318,8 +318,8 @@ struct axppmic_softc {
uint8_t (*sc_read)(struct axppmic_softc *, uint8_t);
void (*sc_write)(struct axppmic_softc *, uint8_t, uint8_t);
- struct axppmic_regdata *sc_regdata;
- struct axppmic_sensdata *sc_sensdata;
+ const struct axppmic_regdata *sc_regdata;
+ const struct axppmic_sensdata *sc_sensdata;
struct ksensor sc_sensor[AXPPMIC_NSENSORS];
struct ksensordev sc_sensordev;
blob - 99d88ed812548c2b2d15c5e9903b133c83617148
blob + 5b5a982cedcc05af187f7d147ad07412431c2dd3
--- sys/dev/fdt/bd718x7.c
+++ sys/dev/fdt/bd718x7.c
@@ -37,12 +37,12 @@ struct bdpmic_regdata {
uint32_t base, delta;
};
-struct bdpmic_regdata bd71837_regdata[] = {
+const struct bdpmic_regdata bd71837_regdata[] = {
{ "BUCK2", 0x10, 0x3f, 700000, 10000 },
{ }
};
-struct bdpmic_regdata bd71847_regdata[] = {
+const struct bdpmic_regdata bd71847_regdata[] = {
{ "BUCK2", 0x10, 0x3f, 700000, 10000 },
{ }
};
@@ -52,7 +52,7 @@ struct bdpmic_softc {
i2c_tag_t sc_tag;
i2c_addr_t sc_addr;
- struct bdpmic_regdata *sc_regdata;
+ const struct bdpmic_regdata *sc_regdata;
};
int bdpmic_match(struct device *, void *, void *);
blob - 509b12e45db5a0c8021b868c467baf86282d9263
blob + 209842677a8c469f5f12df901ccef900e60c4639
--- sys/dev/fdt/hiclock.c
+++ sys/dev/fdt/hiclock.c
@@ -75,7 +75,7 @@ void hi3670_crgctrl_enable(void *, uint32_t *, int);
uint32_t hi3670_stub_get_frequency(void *, uint32_t *);
int hi3670_stub_set_frequency(void *, uint32_t *, uint32_t);
-struct hiclock_compat hiclock_compat[] = {
+const struct hiclock_compat hiclock_compat[] = {
/* Official Linux device tree bindings. */
{
.compat = "hisilicon,hi3670-crgctrl",
blob - 83790e66055bbaad4a340566f9bdc5409b9f7ac3
blob + 1ed33396b43be32bad8591e4404834bf8582ce07
--- sys/dev/fdt/hitemp.c
+++ sys/dev/fdt/hitemp.c
@@ -71,7 +71,7 @@ struct hitemp_compat {
uint64_t hi3660_calc_temp(uint64_t);
uint64_t hi3670_calc_temp(uint64_t);
-struct hitemp_compat hitemp_compat[] = {
+const struct hitemp_compat hitemp_compat[] = {
{
"hsilicon,hi3660-tsensor",
HI3660_OFFSET, hi3660_calc_temp
blob - 26fe4f67e46f90dbe66080375a925f3b880c8ab5
blob + 433e30e47b739809920d4a60fc628d48a1a2e204
--- sys/dev/fdt/imxccm.c
+++ sys/dev/fdt/imxccm.c
@@ -213,13 +213,13 @@ struct imxccm_softc {
struct regmap *sc_anatop;
- struct imxccm_gate *sc_gates;
+ const struct imxccm_gate *sc_gates;
int sc_ngates;
- struct imxccm_divider *sc_divs;
+ const struct imxccm_divider *sc_divs;
int sc_ndivs;
- struct imxccm_mux *sc_muxs;
+ const struct imxccm_mux *sc_muxs;
int sc_nmuxs;
- struct imxccm_divider *sc_predivs;
+ const struct imxccm_divider *sc_predivs;
int sc_npredivs;
struct clock_device sc_cd;
};
blob - a306c2fb7937f35b728a79161e4ba7fa8b1b8164
blob + 5801c4a73528ff4a0edee53d7f3b607a2fa06a06
--- sys/dev/fdt/imxccm_clocks.h
+++ sys/dev/fdt/imxccm_clocks.h
@@ -34,7 +34,7 @@
#define IMX6_CLK_PLL6 0xe4
#define IMX6_CLK_PLL7 0xe5
-struct imxccm_gate imx6_gates[] = {
+const struct imxccm_gate imx6_gates[] = {
[IMX6_CLK_ECSPI2] = { CCM_CCGR1, 1, IMX6_CLK_ECSPI_ROOT },
[IMX6_CLK_ENET] = { CCM_CCGR1, 5, IMX6_CLK_IPG },
[IMX6_CLK_I2C1] = { CCM_CCGR2, 3, IMX6_CLK_IPG_PER },
@@ -69,7 +69,7 @@ struct imxccm_gate imx6_gates[] = {
#define IMX6UL_CLK_USDHC1 0xce
#define IMX6UL_CLK_USDHC2 0xcf
-struct imxccm_gate imx6ul_gates[] = {
+const struct imxccm_gate imx6ul_gates[] = {
[IMX6UL_CLK_GPT1_BUS] = { CCM_CCGR1, 10, IMX6UL_CLK_PERCLK },
[IMX6UL_CLK_GPT1_SERIAL] = { CCM_CCGR1, 11, IMX6UL_CLK_PERCLK },
[IMX6UL_CLK_I2C1] = { CCM_CCGR2, 3, IMX6UL_CLK_PERCLK },
@@ -184,7 +184,7 @@ struct imxccm_gate imx6ul_gates[] = {
#define IMX7D_USB_PHY1_CLK 0x1a7
#define IMX7D_USB_PHY2_CLK 0x1a8
-struct imxccm_gate imx7d_gates[] = {
+const struct imxccm_gate imx7d_gates[] = {
[IMX7D_ENET_AXI_ROOT_CG] = { 0x8900, 28, IMX7D_ENET_AXI_ROOT_SRC },
[IMX7D_ENET1_TIME_ROOT_CG] = { 0xa780, 28, IMX7D_ENET1_TIME_ROOT_SRC },
[IMX7D_ENET2_TIME_ROOT_CG] = { 0xa880, 28, IMX7D_ENET2_TIME_ROOT_SRC },
@@ -227,7 +227,7 @@ struct imxccm_gate imx7d_gates[] = {
[IMX7D_UART7_ROOT_CLK] = { 0x49a0, 0, IMX7D_UART7_ROOT_DIV },
};
-struct imxccm_divider imx7d_divs[] = {
+const struct imxccm_divider imx7d_divs[] = {
[IMX7D_ENET_AXI_ROOT_PRE_DIV] = { 0x8900, 16, 0x7,
IMX7D_ENET_AXI_ROOT_CG },
[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = { 0xa780, 16, 0x7,
IMX7D_ENET1_TIME_ROOT_CG },
[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = { 0xa880, 16, 0x7,
IMX7D_ENET2_TIME_ROOT_CG },
@@ -266,7 +266,7 @@ struct imxccm_divider imx7d_divs[] = {
[IMX7D_UART7_ROOT_DIV] = { 0xb280, 0, 0x3f, IMX7D_UART7_ROOT_PRE_DIV },
};
-struct imxccm_mux imx7d_muxs[] = {
+const struct imxccm_mux imx7d_muxs[] = {
[IMX7D_ENET_AXI_ROOT_SRC] = { 0x8900, 24, 0x7 },
[IMX7D_ENET1_TIME_ROOT_SRC] = { 0xa780, 24, 0x7 },
[IMX7D_ENET2_TIME_ROOT_SRC] = { 0xa880, 24, 0x7 },
@@ -346,7 +346,7 @@ struct imxccm_mux imx7d_muxs[] = {
#define IMX8MM_CLK_TMU_ROOT 0xd1
#define IMX8MM_CLK_ARM 0xd7
-struct imxccm_gate imx8mm_gates[] = {
+const struct imxccm_gate imx8mm_gates[] = {
[IMX8MM_CLK_A53_CG] = { 0x8000, 14 },
[IMX8MM_CLK_ENET_AXI] = { 0x8880, 14 },
[IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 14 },
@@ -392,7 +392,7 @@ struct imxccm_gate imx8mm_gates[] = {
[IMX8MM_CLK_TMU_ROOT] = { 0x4620, 0 },
};
-struct imxccm_divider imx8mm_divs[] = {
+const struct imxccm_divider imx8mm_divs[] = {
[IMX8MM_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MM_CLK_A53_CG },
[IMX8MM_CLK_ENET_AXI] = { 0x8880, 0, 0x3f },
[IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f },
@@ -420,7 +420,7 @@ struct imxccm_divider imx8mm_divs[] = {
[IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 0, 0x3f },
};
-struct imxccm_divider imx8mm_predivs[] = {
+const struct imxccm_divider imx8mm_predivs[] = {
[IMX8MM_CLK_ENET_AXI] = { 0x8880, 16, 0x7 },
[IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 },
[IMX8MM_CLK_USB_BUS] = { 0x8b80, 16, 0x7 },
@@ -446,7 +446,7 @@ struct imxccm_divider imx8mm_predivs[] = {
[IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 16, 0x7 },
};
-struct imxccm_mux imx8mm_muxs[] = {
+const struct imxccm_mux imx8mm_muxs[] = {
[IMX8MM_CLK_A53_SRC] = { 0x8000, 24, 0x7 },
[IMX8MM_CLK_ENET_AXI] = { 0x8880, 24, 0x7 },
[IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 },
@@ -535,7 +535,7 @@ struct imxccm_mux imx8mm_muxs[] = {
#define IMX8MP_CLK_USDHC3_ROOT 0x115
#define IMX8MP_CLK_HSIO_AXI 0x137
-struct imxccm_gate imx8mp_gates[] = {
+const struct imxccm_gate imx8mp_gates[] = {
[IMX8MP_CLK_ENET_AXI] = { 0x8880, 14 },
[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 14 },
[IMX8MP_CLK_AHB] = { 0x9000, 14 },
@@ -588,7 +588,7 @@ struct imxccm_gate imx8mp_gates[] = {
[IMX8MP_CLK_HSIO_AXI] = { 0x8400, 14 },
};
-struct imxccm_divider imx8mp_divs[] = {
+const struct imxccm_divider imx8mp_divs[] = {
[IMX8MP_CLK_ENET_AXI] = { 0x8880, 0, 0x3f },
[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f },
[IMX8MP_CLK_AHB] = { 0x9000, 0, 0x3f },
@@ -620,7 +620,7 @@ struct imxccm_divider imx8mp_divs[] = {
[IMX8MP_CLK_HSIO_AXI] = { 0x8400, 0, 0x3f },
};
-struct imxccm_divider imx8mp_predivs[] = {
+const struct imxccm_divider imx8mp_predivs[] = {
[IMX8MP_CLK_ENET_AXI] = { 0x8880, 16, 0x7 },
[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 },
[IMX8MP_CLK_AHB] = { 0x9000, 16, 0x7 },
@@ -651,7 +651,7 @@ struct imxccm_divider imx8mp_predivs[] = {
[IMX8MP_CLK_HSIO_AXI] = { 0x8400, 16, 0x7 },
};
-struct imxccm_mux imx8mp_muxs[] = {
+const struct imxccm_mux imx8mp_muxs[] = {
[IMX8MP_CLK_ENET_AXI] = { 0x8880, 24, 0x7 },
[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 },
[IMX8MP_CLK_AHB] = { 0x9000, 24, 0x7 },
@@ -760,7 +760,7 @@ struct imxccm_mux imx8mp_muxs[] = {
#define IMX8MQ_CLK_OCOTP_ROOT 0xfa
#define IMX8MQ_CLK_ARM 0x102
-struct imxccm_gate imx8mq_gates[] = {
+const struct imxccm_gate imx8mq_gates[] = {
[IMX8MQ_CLK_A53_CG] = { 0x8000, 14 },
[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 14 },
[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 14 },
@@ -822,7 +822,7 @@ struct imxccm_gate imx8mq_gates[] = {
[IMX8MQ_CLK_OCOTP_ROOT] = { 0x4220, 0, IMX8MQ_CLK_IPG_ROOT },
};
-struct imxccm_divider imx8mq_divs[] = {
+const struct imxccm_divider imx8mq_divs[] = {
[IMX8MQ_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MQ_CLK_A53_CG },
[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 0, 0x3f },
[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f },
@@ -859,7 +859,7 @@ struct imxccm_divider imx8mq_divs[] = {
[IMX8MQ_CLK_IPG_ROOT] = { 0x9080, 0, 0x1, IMX8MQ_CLK_AHB },
};
-struct imxccm_divider imx8mq_predivs[] = {
+const struct imxccm_divider imx8mq_predivs[] = {
[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 16, 0x7 },
[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 },
[IMX8MQ_CLK_USB_BUS] = { 0x8b80, 16, 0x7 },
@@ -894,7 +894,7 @@ struct imxccm_divider imx8mq_predivs[] = {
[IMX8MQ_CLK_ECSPI3] = { 0xc180, 16, 0x7 },
};
-struct imxccm_mux imx8mq_muxs[] = {
+const struct imxccm_mux imx8mq_muxs[] = {
[IMX8MQ_CLK_A53_SRC] = { 0x8000, 24, 0x7 },
[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 24, 0x7 },
[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 },
blob - 3bee1a00c6fff3b4207cc192bdc82e2f827bff2c
blob + 6d9b2d5236c0e0d5472d1bbf1036c1d60b30fd2f
--- sys/dev/fdt/imxsrc.c
+++ sys/dev/fdt/imxsrc.c
@@ -62,7 +62,7 @@ struct imxsrc_reset {
uint32_t bit;
};
-struct imxsrc_reset imx51_resets[] = {
+const struct imxsrc_reset imx51_resets[] = {
[IMX51_RESET_GPU] = { SRC_SCR, SRC_SCR_SW_GPU_RST },
[IMX51_RESET_VPU] = { SRC_SCR, SRC_SCR_SW_VPU_RST },
[IMX51_RESET_IPU1] = { SRC_SCR, SRC_SCR_SW_IPU1_RST },
@@ -70,7 +70,7 @@ struct imxsrc_reset imx51_resets[] = {
[IMX51_RESET_IPU2] = { SRC_SCR, SRC_SCR_SW_IPU2_RST },
};
-struct imxsrc_reset imx8m_resets[] = {
+const struct imxsrc_reset imx8m_resets[] = {
[IMX8M_RESET_PCIEPHY] = { SRC_PCIE1_RCR,
SRC_PCIE_RCR_PCIEPHY_G_RST | SRC_PCIE_RCR_PCIEPHY_BTN },
[IMX8M_RESET_PCIEPHY_PERST] = { SRC_PCIE1_RCR,
@@ -103,7 +103,7 @@ struct imxsrc_softc {
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
struct reset_device sc_rd;
- struct imxsrc_reset *sc_resets;
+ const struct imxsrc_reset *sc_resets;
int sc_nresets;
};
blob - e30ba6278181cbd6fb002e5fa9b709b0402a4276
blob + baed602d93febfa523a996eef8244b69e7636f25
--- sys/dev/fdt/mvpinctrl.c
+++ sys/dev/fdt/mvpinctrl.c
@@ -47,8 +47,8 @@
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
struct mvpinctrl_pin {
- char *pin;
- char *function;
+ const char *pin;
+ const char *function;
int value;
int pid;
};
@@ -58,7 +58,7 @@ struct mvpinctrl_softc {
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
struct regmap *sc_rm;
- struct mvpinctrl_pin *sc_pins;
+ const struct mvpinctrl_pin *sc_pins;
int sc_npins;
struct gpio_controller sc_gc;
struct clock_device sc_cd_xtal;
@@ -90,11 +90,11 @@ struct cfdriver mvpinctrl_cd = {
struct mvpinctrl_pins {
const char *compat;
- struct mvpinctrl_pin *pins;
+ const struct mvpinctrl_pin *pins;
int npins;
};
-struct mvpinctrl_pins mvpinctrl_pins[] = {
+const struct mvpinctrl_pins mvpinctrl_pins[] = {
{
"marvell,mv88f6810-pinctrl",
armada_38x_pins, nitems(armada_38x_pins)
blob - c9249cfe63d00e0c9a6ffd7abd0b78ed9019b3ba
blob + 243a27a7c05f8489535fbbcab00b00b69faa662a
--- sys/dev/fdt/mvpinctrl_pins.h
+++ sys/dev/fdt/mvpinctrl_pins.h
@@ -1,7 +1,7 @@
/* Public Domain */
-struct mvpinctrl_pin armada_38x_pins[] = {
+const struct mvpinctrl_pin armada_38x_pins[] = {
MPP(0, "gpio", 0),
MPP(0, "ua0", 1),
MPP(1, "gpio", 0),
@@ -290,7 +290,7 @@ struct mvpinctrl_pin armada_38x_pins[] = {
MPP(59, "sd0", 5),
};
-struct mvpinctrl_pin armada_ap806_pins[] = {
+const struct mvpinctrl_pin armada_ap806_pins[] = {
MPP(0, "gpio", 0),
MPP(0, "sdio", 1),
MPP(0, "spi0", 3),
@@ -338,7 +338,7 @@ struct mvpinctrl_pin armada_ap806_pins[] = {
MPP(19, "sdio", 4),
};
-struct mvpinctrl_pin armada_cp110_pins[] = {
+const struct mvpinctrl_pin armada_cp110_pins[] = {
MPP(0, "gpio", 0),
MPP(0, "dev", 1),
MPP(0, "au", 2),
blob - 07cd50ac9829ad884fd1d371a0367fecedb00b1f
blob + 3b0d209662473562a0f4e14420929119107a3c1c
--- sys/dev/fdt/mvtemp.c
+++ sys/dev/fdt/mvtemp.c
@@ -70,7 +70,7 @@ int32_t mvtemp_ap806_calc_temp(uint32_t);
void mvtemp_cp110_init(struct mvtemp_softc *);
int32_t mvtemp_cp110_calc_temp(uint32_t);
-struct mvtemp_compat mvtemp_compat[] = {
+const struct mvtemp_compat mvtemp_compat[] = {
{
"marvell,armada-ap806-thermal", (1 << 16),
mvtemp_ap806_init, mvtemp_ap806_calc_temp,
blob - e0b84f4d1518a9c57f477c84bf2d2f4253a5ca19
blob + a1c6a6e97269c69f2304d1b4c70749782492e942
--- sys/dev/fdt/rkclock.c
+++ sys/dev/fdt/rkclock.c
@@ -203,7 +203,7 @@ struct rkclock_softc {
struct regmap *sc_grf;
uint32_t sc_phandle;
- struct rkclock *sc_clocks;
+ const struct rkclock *sc_clocks;
struct clock_device sc_cd;
struct reset_device sc_rd;
@@ -264,7 +264,7 @@ struct rkclock_compat {
void (*reset)(void *, uint32_t *, int);
};
-struct rkclock_compat rkclock_compat[] = {
+const struct rkclock_compat rkclock_compat[] = {
{
"rockchip,rk3288-cru", 0, rk3288_init,
rk3288_enable, rk3288_get_frequency,
@@ -365,10 +365,10 @@ rkclock_attach(struct device *parent, struct device *s
clock_set_assigned(faa->fa_node);
}
-struct rkclock *
+const struct rkclock *
rkclock_lookup(struct rkclock_softc *sc, uint32_t idx)
{
- struct rkclock *clk;
+ const struct rkclock *clk;
for (clk = sc->sc_clocks; clk->idx; clk++) {
if (clk->idx == idx)
@@ -379,7 +379,7 @@ rkclock_lookup(struct rkclock_softc *sc, uint32_t idx)
}
uint32_t
-rkclock_div_con(struct rkclock_softc *sc, struct rkclock *clk,
+rkclock_div_con(struct rkclock_softc *sc, const struct rkclock *clk,
uint32_t mux, uint32_t freq)
{
uint32_t parent_freq, div, div_con, max_div_con;
@@ -395,7 +395,7 @@ rkclock_div_con(struct rkclock_softc *sc, struct rkclo
}
uint32_t
-rkclock_freq(struct rkclock_softc *sc, struct rkclock *clk,
+rkclock_freq(struct rkclock_softc *sc, const struct rkclock *clk,
uint32_t mux, uint32_t freq)
{
uint32_t parent_freq, div_con;
@@ -409,7 +409,7 @@ rkclock_freq(struct rkclock_softc *sc, struct rkclock
uint32_t
rkclock_get_frequency(struct rkclock_softc *sc, uint32_t idx)
{
- struct rkclock *clk;
+ const struct rkclock *clk;
uint32_t reg, mux, div_con;
int shift;
@@ -442,7 +442,7 @@ rkclock_get_frequency(struct rkclock_softc *sc, uint32
int
rkclock_set_frequency(struct rkclock_softc *sc, uint32_t idx, uint32_t freq)
{
- struct rkclock *clk;
+ const struct rkclock *clk;
uint32_t reg, mux, div_con;
uint32_t best_freq, best_mux, f;
int sel_shift, div_shift, i;
@@ -512,7 +512,7 @@ rkclock_set_frequency(struct rkclock_softc *sc, uint32
int
rkclock_set_parent(struct rkclock_softc *sc, uint32_t idx, uint32_t parent)
{
- struct rkclock *clk;
+ const struct rkclock *clk;
uint32_t mux;
int shift;
@@ -540,7 +540,7 @@ rkclock_set_parent(struct rkclock_softc *sc, uint32_t
* Rockchip RK3288
*/
-struct rkclock rk3288_clocks[] = {
+const struct rkclock rk3288_clocks[] = {
{
RK3288_CLK_SDMMC, RK3288_CRU_CLKSEL_CON(11),
SEL(7, 6), DIV(5, 0),
@@ -861,7 +861,7 @@ rk3288_reset(void *cookie, uint32_t *cells, int on)
* Rockchip RK3308
*/
-struct rkclock rk3308_clocks[] = {
+const struct rkclock rk3308_clocks[] = {
{
RK3308_CLK_RTC32K, RK3308_CRU_CLKSEL_CON(2),
SEL(10, 9), 0,
@@ -1261,7 +1261,7 @@ rk3308_get_rtc32k(struct rkclock_softc *sc)
int
rk3308_set_rtc32k(struct rkclock_softc *sc, uint32_t freq)
{
- struct rkclock *clk;
+ const struct rkclock *clk;
uint32_t vpll0_freq, vpll1_freq, mux, div_con;
clk = rkclock_lookup(sc, RK3308_CLK_RTC32K);
@@ -1384,7 +1384,7 @@ rk3308_reset(void *cookie, uint32_t *cells, int on)
* Rockchip RK3328
*/
-struct rkclock rk3328_clocks[] = {
+const struct rkclock rk3328_clocks[] = {
{
RK3328_CLK_RTC32K, RK3328_CRU_CLKSEL_CON(38),
SEL(15, 14), DIV(13, 0),
@@ -2089,7 +2089,7 @@ rk3328_reset(void *cookie, uint32_t *cells, int on)
* Rockchip RK3399
*/
-struct rkclock rk3399_clocks[] = {
+const struct rkclock rk3399_clocks[] = {
{
RK3399_CLK_I2C1, RK3399_CRU_CLKSEL_CON(61),
SEL(7, 7), DIV(6, 0),
@@ -2844,7 +2844,7 @@ rk3399_reset(void *cookie, uint32_t *cells, int on)
/* PMUCRU */
-struct rkclock rk3399_pmu_clocks[] = {
+const struct rkclock rk3399_pmu_clocks[] = {
{
RK3399_CLK_I2C0, RK3399_PMUCRU_CLKSEL_CON(2),
0, DIV(6, 0),
blob - 2226c91bd424ace0ff73e3b863e5c11446b30d47
blob + 96fa316f92aa0fba7279afb62dd6066453e94112
--- sys/dev/fdt/rkpinctrl.c
+++ sys/dev/fdt/rkpinctrl.c
@@ -596,7 +596,7 @@ rk3399_pull(uint32_t bank, uint32_t idx, uint32_t phan
/* Magic because the drive strength configurations vary wildly. */
-int rk3399_strength_levels[][8] = {
+const int rk3399_strength_levels[][8] = {
{ 2, 4, 8, 12 }, /* default */
{ 3, 6, 9, 12 }, /* 1.8V or 3.0V */
{ 5, 10, 15, 20 }, /* 1.8V only */
@@ -604,7 +604,7 @@ int rk3399_strength_levels[][8] = {
{ 4, 7, 10, 13, 16, 19, 22, 26 }, /* 3.3V */
};
-int rk3399_strength_types[][4] = {
+const int rk3399_strength_types[][4] = {
{ 2, 2, 0, 0 },
{ 1, 1, 1, 1 },
{ 1, 1, 2, 2 },
@@ -612,7 +612,7 @@ int rk3399_strength_types[][4] = {
{ 1, 3, 1, 1 },
};
-int rk3399_strength_regs[][4] = {
+const int rk3399_strength_regs[][4] = {
{ 0x0080, 0x0088, 0x0090, 0x0098 },
{ 0x00a0, 0x00a8, 0x00b0, 0x00b8 },
{ 0x0100, 0x0104, 0x0108, 0x010c },
@@ -624,7 +624,7 @@ int
rk3399_strength(uint32_t bank, uint32_t idx, uint32_t phandle)
{
int strength, type, level;
- int *levels;
+ const int *levels;
int node;
node = OF_getnodebyphandle(phandle);
blob - cbda91d3258efcf641d35a8a7d8fe98dceeecede
blob + d96a053324950e8584fdeb961acd7c4cd76141b8
--- sys/dev/fdt/rkpmic.c
+++ sys/dev/fdt/rkpmic.c
@@ -57,7 +57,7 @@ struct rkpmic_vsel_range {
struct rkpmic_regdata {
const char *name;
uint8_t reg, mask;
- struct rkpmic_vsel_range *vsel_range;
+ const struct rkpmic_vsel_range *vsel_range;
};
/*
@@ -66,7 +66,7 @@ struct rkpmic_regdata {
* 60-62: 1.8V-2.2V, step=200mV
* 63: 2.3V
*/
-struct rkpmic_vsel_range rk805_vsel_range1[] = {
+const struct rkpmic_vsel_range rk805_vsel_range1[] = {
{ 712500, 12500, 0, 59 },
{ 1800000, 200000, 60, 62 },
{ 2300000, 0, 63, 63 },
@@ -77,7 +77,7 @@ struct rkpmic_vsel_range rk805_vsel_range1[] = {
* Used by RK805 for BUCK4
* 0-27: 0.8V-3.5V, step=100mV
*/
-struct rkpmic_vsel_range rk805_vsel_range2[] = {
+const struct rkpmic_vsel_range rk805_vsel_range2[] = {
{ 800000, 100000, 0, 27 },
{}
};
@@ -86,12 +86,12 @@ struct rkpmic_vsel_range rk805_vsel_range2[] = {
* Used by RK805 for LDO1-3
* 0-26: 0.8V-3.4V, step=100mV
*/
-struct rkpmic_vsel_range rk805_vsel_range3[] = {
+const struct rkpmic_vsel_range rk805_vsel_range3[] = {
{ 800000, 100000, 0, 26 },
{}
};
-struct rkpmic_regdata rk805_regdata[] = {
+const struct rkpmic_regdata rk805_regdata[] = {
{ "DCDC_REG1", 0x2f, 0x3f, rk805_vsel_range1 },
{ "DCDC_REG2", 0x33, 0x3f, rk805_vsel_range1 },
{ "DCDC_REG4", 0x38, 0x1f, rk805_vsel_range2 },
@@ -105,7 +105,7 @@ struct rkpmic_regdata rk805_regdata[] = {
* Used by RK808 for BUCK1 & BUCK2
* 0-63: 0.7125V-1.5V, step=12.5mV
*/
-struct rkpmic_vsel_range rk808_vsel_range1[] = {
+const struct rkpmic_vsel_range rk808_vsel_range1[] = {
{ 712500, 12500, 0, 63 },
{}
};
@@ -114,7 +114,7 @@ struct rkpmic_vsel_range rk808_vsel_range1[] = {
* Used by RK808 for BUCK4
* 0-15: 1.8V-3.3V,step=100mV
*/
-struct rkpmic_vsel_range rk808_vsel_range2[] = {
+const struct rkpmic_vsel_range rk808_vsel_range2[] = {
{ 1800000, 100000, 0, 15 },
{}
};
@@ -123,7 +123,7 @@ struct rkpmic_vsel_range rk808_vsel_range2[] = {
* Used by RK808 for LDO1-2, 4-5, 8
* 0-16: 1.8V-3.4V, step=100mV
*/
-struct rkpmic_vsel_range rk808_vsel_range3[] = {
+const struct rkpmic_vsel_range rk808_vsel_range3[] = {
{ 1800000, 100000, 0, 16 },
{}
};
@@ -134,7 +134,7 @@ struct rkpmic_vsel_range rk808_vsel_range3[] = {
* 13: 2.2V
* 15: 2.5V
*/
-struct rkpmic_vsel_range rk808_vsel_range4[] = {
+const struct rkpmic_vsel_range rk808_vsel_range4[] = {
{ 800000, 100000, 0, 12 },
{ 2200000, 0, 13, 13 },
{ 2500000, 0, 15, 15 },
@@ -145,12 +145,12 @@ struct rkpmic_vsel_range rk808_vsel_range4[] = {
* Used by RK808 for LDO6-7
* 0-17: 0.8V-2.5V,step=100mV
*/
-struct rkpmic_vsel_range rk808_vsel_range5[] = {
+const struct rkpmic_vsel_range rk808_vsel_range5[] = {
{ 800000, 100000, 0, 17 },
{}
};
-struct rkpmic_regdata rk808_regdata[] = {
+const struct rkpmic_regdata rk808_regdata[] = {
{ "DCDC_REG1", 0x2f, 0x3f, rk808_vsel_range1 },
{ "DCDC_REG2", 0x33, 0x3f, rk808_vsel_range1 },
{ "DCDC_REG4", 0x38, 0x0f, rk808_vsel_range2 },
@@ -170,7 +170,7 @@ struct rkpmic_regdata rk808_regdata[] = {
* 0-80: 0.5V-1.5V,step=12.5mV
* 81-89: 1.6V-2.4V,step=100mV
*/
-struct rkpmic_vsel_range rk809_vsel_range1[] = {
+const struct rkpmic_vsel_range rk809_vsel_range1[] = {
{ 500000, 12500, 0, 80 },
{ 1600000, 100000, 81, 89 },
{}
@@ -181,7 +181,7 @@ struct rkpmic_vsel_range rk809_vsel_range1[] = {
* 0-80: 0.5V-1.5V,step=12.5mV
* 81-99: 1.6V-3.4V,step=100mV
*/
-struct rkpmic_vsel_range rk809_vsel_range2[] = {
+const struct rkpmic_vsel_range rk809_vsel_range2[] = {
{ 500000, 12500, 0, 80 },
{ 1600000, 100000, 81, 99 },
{}
@@ -194,7 +194,7 @@ struct rkpmic_vsel_range rk809_vsel_range2[] = {
* 4-5: 2.8V-3.0V,step=200mV
* 6-7: 3.3V-3.6V,step=300mV
*/
-struct rkpmic_vsel_range rk809_vsel_range3[] = {
+const struct rkpmic_vsel_range rk809_vsel_range3[] = {
{ 1500000, 0, 0, 0 },
{ 1800000, 200000, 1, 3 },
{ 2800000, 200000, 4, 5 },
@@ -206,12 +206,12 @@ struct rkpmic_vsel_range rk809_vsel_range3[] = {
* Used by RK809 for LDO1-7
* 0-112: 0.6V-3.4V,step=25mV
*/
-struct rkpmic_vsel_range rk809_vsel_range4[] = {
+const struct rkpmic_vsel_range rk809_vsel_range4[] = {
{ 600000, 25000, 0, 112 },
{}
};
-struct rkpmic_regdata rk809_regdata[] = {
+const struct rkpmic_regdata rk809_regdata[] = {
{ "DCDC_REG1", 0xbb, 0x7f, rk809_vsel_range1 },
{ "DCDC_REG2", 0xbe, 0x7f, rk809_vsel_range1 },
{ "DCDC_REG3", 0xc1, 0x7f, rk809_vsel_range1 },
@@ -236,7 +236,7 @@ struct rkpmic_softc {
int sc_rtc_ctrl_reg, sc_rtc_status_reg;
struct todr_chip_handle sc_todr;
- struct rkpmic_regdata *sc_regdata;
+ const struct rkpmic_regdata *sc_regdata;
};
int rkpmic_match(struct device *, void *, void *);
@@ -314,7 +314,7 @@ struct rkpmic_regulator {
struct rkpmic_softc *rr_sc;
uint8_t rr_reg, rr_mask;
- struct rkpmic_vsel_range *rr_vsel_range;
+ const struct rkpmic_vsel_range *rr_vsel_range;
struct regulator_device rr_rd;
};
@@ -357,7 +357,7 @@ uint32_t
rkpmic_get_voltage(void *cookie)
{
struct rkpmic_regulator *rr = cookie;
- struct rkpmic_vsel_range *vsel_range = rr->rr_vsel_range;
+ const struct rkpmic_vsel_range *vsel_range = rr->rr_vsel_range;
uint8_t vsel;
uint32_t ret = 0;
@@ -384,7 +384,7 @@ int
rkpmic_set_voltage(void *cookie, uint32_t voltage)
{
struct rkpmic_regulator *rr = cookie;
- struct rkpmic_vsel_range *vsel_range = rr->rr_vsel_range;
+ const struct rkpmic_vsel_range *vsel_range = rr->rr_vsel_range;
uint32_t vmin, vmax, volt;
uint8_t reg, vsel;
blob - f067e0c018d65fb33af681c302c07e02c5875596
blob + 7a8e94430d1cb6681359a4c351d2818ad82ea063
--- sys/dev/fdt/rktemp.c
+++ sys/dev/fdt/rktemp.c
@@ -77,7 +77,7 @@ struct rktemp_entry {
};
/* RK3288 conversion table. */
-struct rktemp_entry rk3288_temps[] = {
+const struct rktemp_entry rk3288_temps[] = {
{ -40000, 3800 },
{ -35000, 3792 },
{ -30000, 3783 },
@@ -114,10 +114,10 @@ struct rktemp_entry rk3288_temps[] = {
{ 125000, 3421 },
};
-const char *rk3288_names[] = { "", "CPU", "GPU" };
+const char *const rk3288_names[] = { "", "CPU", "GPU" };
/* RK3328 conversion table. */
-struct rktemp_entry rk3328_temps[] = {
+const struct rktemp_entry rk3328_temps[] = {
{ -40000, 296 },
{ -35000, 304 },
{ -30000, 313 },
@@ -153,11 +153,11 @@ struct rktemp_entry rk3328_temps[] = {
{ 125000, 675 },
};
-const char *rk3308_names[] = { "CPU", "GPU" };
-const char *rk3328_names[] = { "CPU" };
+const char *const rk3308_names[] = { "CPU", "GPU" };
+const char *const rk3328_names[] = { "CPU" };
/* RK3399 conversion table. */
-struct rktemp_entry rk3399_temps[] = {
+const struct rktemp_entry rk3399_temps[] = {
{ -40000, 402 },
{ -35000, 410 },
{ -30000, 419 },
@@ -194,14 +194,14 @@ struct rktemp_entry rk3399_temps[] = {
{ 125000, 685 },
};
-const char *rk3399_names[] = { "CPU", "GPU" };
+const char *const rk3399_names[] = { "CPU", "GPU" };
struct rktemp_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
- struct rktemp_entry *sc_temps;
+ const struct rktemp_entry *sc_temps;
int sc_ntemps;
struct ksensor sc_sensors[3];
@@ -244,7 +244,7 @@ rktemp_attach(struct device *parent, struct device *se
{
struct rktemp_softc *sc = (struct rktemp_softc *)self;
struct fdt_attach_args *faa = aux;
- const char **names;
+ const char *const *names;
uint32_t mode, polarity, temp;
uint32_t auto_con, int_en;
int node = faa->fa_node;
blob - 140473537fa73786acf1d1e3fe5a55a1d82dae49
blob + 43f9c445cf97cd9cd371310df4179853c714a282
--- sys/dev/fdt/sxiccmu.c
+++ sys/dev/fdt/sxiccmu.c
@@ -58,11 +58,11 @@ struct sxiccmu_softc {
bus_space_handle_t sc_ioh;
int sc_node;
- struct sxiccmu_ccu_bit *sc_gates;
+ const struct sxiccmu_ccu_bit *sc_gates;
int sc_ngates;
struct clock_device sc_cd;
- struct sxiccmu_ccu_bit *sc_resets;
+ const struct sxiccmu_ccu_bit *sc_resets;
int sc_nresets;
struct reset_device sc_rd;
@@ -335,7 +335,7 @@ void sxiccmu_mmc_enable(void *, uint32_t *, int);
void sxiccmu_gate_enable(void *, uint32_t *, int);
void sxiccmu_reset(void *, uint32_t *, int);
-struct sxiccmu_device sxiccmu_devices[] = {
+const struct sxiccmu_device sxiccmu_devices[] = {
{
.compat = "allwinner,sun4i-a10-osc-clk",
.get_frequency = sxiccmu_osc_get_frequency,
blob - 017928faafca34b1cd6dae3e5d963ffae434fa3d
blob + 041162d0ee400f59e101c8b77741bf49e3888ed3
--- sys/dev/fdt/sxiccmu_clocks.h
+++ sys/dev/fdt/sxiccmu_clocks.h
@@ -54,7 +54,7 @@
#define A10_CLK_LOSC 254
-struct sxiccmu_ccu_bit sun4i_a10_gates[] = {
+const struct sxiccmu_ccu_bit sun4i_a10_gates[] = {
[A10_CLK_AHB_EHCI0] = { 0x0060, 1 },
[A10_CLK_AHB_OHCI0] = { 0x0060, 2 },
[A10_CLK_AHB_EHCI1] = { 0x0060, 3 },
@@ -119,7 +119,7 @@ struct sxiccmu_ccu_bit sun4i_a10_gates[] = {
#define A23_CLK_MMC2 66
#define A23_CLK_USB_OHCI 78
-struct sxiccmu_ccu_bit sun8i_a23_gates[] = {
+const struct sxiccmu_ccu_bit sun8i_a23_gates[] = {
[A23_CLK_BUS_MMC0] = { 0x0060, 8 },
[A23_CLK_BUS_MMC1] = { 0x0060, 9 },
[A23_CLK_BUS_MMC2] = { 0x0060, 10 },
@@ -186,7 +186,7 @@ struct sxiccmu_ccu_bit sun8i_a23_gates[] = {
#define A64_CLK_LOSC 254
#define A64_CLK_HOSC 253
-struct sxiccmu_ccu_bit sun50i_a64_gates[] = {
+const struct sxiccmu_ccu_bit sun50i_a64_gates[] = {
[A64_CLK_PLL_PERIPH0] = { 0x0028, 31 },
[A64_CLK_BUS_MMC0] = { 0x0060, 8 },
[A64_CLK_BUS_MMC1] = { 0x0060, 9 },
@@ -246,7 +246,7 @@ struct sxiccmu_ccu_bit sun50i_a64_gates[] = {
#define A80_CLK_BUS_UART4 128
#define A80_CLK_BUS_UART5 129
-struct sxiccmu_ccu_bit sun9i_a80_gates[] = {
+const struct sxiccmu_ccu_bit sun9i_a80_gates[] = {
[A80_CLK_MMC0] = { 0x0410, 31 },
[A80_CLK_MMC1] = { 0x0414, 31 },
[A80_CLK_MMC2] = { 0x0418, 31 },
@@ -281,7 +281,7 @@ struct sxiccmu_ccu_bit sun9i_a80_gates[] = {
#define A80_USB_CLK_HCI2_UTMIPHY 9
#define A80_USB_CLK_HCI1_HSIC_12M 10
-struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = {
+const struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = {
[A80_USB_CLK_HCI0] = { 0x0000, 1 },
[A80_USB_CLK_OHCI0] = { 0x0000, 2 },
[A80_USB_CLK_HCI1] = { 0x0000, 3 },
@@ -295,7 +295,7 @@ struct sxiccmu_ccu_bit sun9i_a80_usb_gates[] = {
[A80_USB_CLK_HCI1_HSIC_12M] = { 0x0004, 10 },
};
-struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
+const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
{ 0x0000, 16 },
{ 0x0004, 16 },
{ 0x0008, 16 },
@@ -353,7 +353,7 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
#define H3_CLK_LOSC 254
#define H3_CLK_HOSC 253
-struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
+const struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
[H3_CLK_PLL_PERIPH0] = { 0x0028, 31 },
[H3_CLK_BUS_MMC0] = { 0x0060, 8 },
[H3_CLK_BUS_MMC1] = { 0x0060, 9 },
@@ -398,7 +398,7 @@ struct sxiccmu_ccu_bit sun8i_h3_gates[] = {
#define H3_R_CLK_APB0_RSB 6
#define H3_R_CLK_APB0_I2C 9
-struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = {
+const struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = {
[H3_R_CLK_APB0_PIO] = { 0x0028, 0 },
[H3_R_CLK_APB0_RSB] = { 0x0028, 3, H3_R_CLK_APB0 },
[H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 },
@@ -432,7 +432,7 @@ struct sxiccmu_ccu_bit sun8i_h3_r_gates[] = {
#define H6_CLK_BUS_EHCI0 113
#define H6_CLK_BUS_EHCI3 115
-struct sxiccmu_ccu_bit sun50i_h6_gates[] = {
+const struct sxiccmu_ccu_bit sun50i_h6_gates[] = {
[H6_CLK_PLL_PERIPH0] = { 0x0020, 31 },
[H6_CLK_APB1] = { 0xffff, 0xff },
[H6_CLK_MMC0] = { 0x0830, 31 },
@@ -462,7 +462,7 @@ struct sxiccmu_ccu_bit sun50i_h6_gates[] = {
#define H6_R_CLK_APB2_I2C 8
#define H6_R_CLK_APB2_RSB 13
-struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = {
+const struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = {
[H6_R_CLK_APB1] = { 0xffff, 0xff },
[H6_R_CLK_APB2_I2C] = { 0x019c, 0, H6_R_CLK_APB2 },
[H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 },
@@ -521,7 +521,7 @@ struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = {
#define R40_CLK_HOSC 253
#define R40_CLK_LOSC 254
-struct sxiccmu_ccu_bit sun8i_r40_gates[] = {
+const struct sxiccmu_ccu_bit sun8i_r40_gates[] = {
[R40_CLK_BUS_MMC0] = { 0x0060, 8 },
[R40_CLK_BUS_MMC1] = { 0x0060, 9 },
[R40_CLK_BUS_MMC2] = { 0x0060, 10 },
@@ -594,7 +594,7 @@ struct sxiccmu_ccu_bit sun8i_r40_gates[] = {
#define V3S_CLK_LOSC 254
#define V3S_CLK_HOSC 253
-struct sxiccmu_ccu_bit sun8i_v3s_gates[] = {
+const struct sxiccmu_ccu_bit sun8i_v3s_gates[] = {
[V3S_CLK_BUS_OHCI0] = { 0x0060, 29 },
[V3S_CLK_BUS_EHCI0] = { 0x0060, 26 },
[V3S_CLK_BUS_EMAC] = { 0x0060, 17, V3S_CLK_AHB2 },
@@ -625,7 +625,7 @@ struct sxiccmu_ccu_bit sun8i_v3s_gates[] = {
#define A10_RST_USB_PHY1 2
#define A10_RST_USB_PHY2 3
-struct sxiccmu_ccu_bit sun4i_a10_resets[] = {
+const struct sxiccmu_ccu_bit sun4i_a10_resets[] = {
[A10_RST_USB_PHY0] = { 0x00cc, 0 },
[A10_RST_USB_PHY1] = { 0x00cc, 1 },
[A10_RST_USB_PHY2] = { 0x00cc, 2 },
@@ -650,7 +650,7 @@ struct sxiccmu_ccu_bit sun4i_a10_resets[] = {
#define A23_CLK_HOSC 253
#define A23_CLK_LOSC 254
-struct sxiccmu_ccu_bit sun8i_a23_resets[] = {
+const struct sxiccmu_ccu_bit sun8i_a23_resets[] = {
[A23_RST_USB_PHY0] = { 0x00cc, 0 },
[A23_RST_USB_PHY1] = { 0x00cc, 1 },
[A23_RST_BUS_MMC0] = { 0x02c0, 8 },
@@ -686,7 +686,7 @@ struct sxiccmu_ccu_bit sun8i_a23_resets[] = {
#define A64_RST_BUS_UART3 49
#define A64_RST_BUS_UART4 50
-struct sxiccmu_ccu_bit sun50i_a64_resets[] = {
+const struct sxiccmu_ccu_bit sun50i_a64_resets[] = {
[A64_RST_USB_PHY0] = { 0x00cc, 0 },
[A64_RST_USB_PHY1] = { 0x00cc, 1 },
[A64_RST_BUS_MMC0] = { 0x02c0, 8 },
@@ -724,7 +724,7 @@ struct sxiccmu_ccu_bit sun50i_a64_resets[] = {
#define A80_RST_BUS_UART4 49
#define A80_RST_BUS_UART5 50
-struct sxiccmu_ccu_bit sun9i_a80_resets[] = {
+const struct sxiccmu_ccu_bit sun9i_a80_resets[] = {
[A80_RST_BUS_MMC] = { 0x05a0, 8 },
[A80_RST_BUS_GMAC] = { 0x05a4, 17 },
[A80_RST_BUS_I2C0] = { 0x05b4, 0 },
@@ -750,7 +750,7 @@ struct sxiccmu_ccu_bit sun9i_a80_resets[] = {
#define A80_USB_RST_HCI2_HSIC 6
#define A80_USB_RST_HCI2_UTMIPHY 7
-struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = {
+const struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = {
[A80_USB_RST_HCI0] = { 0x0000, 17 },
[A80_USB_RST_HCI1] = { 0x0000, 18 },
[A80_USB_RST_HCI2] = { 0x0000, 19 },
@@ -761,7 +761,7 @@ struct sxiccmu_ccu_bit sun9i_a80_usb_resets[] = {
[A80_USB_RST_HCI2_UTMIPHY] = { 0x0004, 21 },
};
-struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
+const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
{ 0x0000, 18 },
{ 0x0004, 18 },
{ 0x0008, 18 },
@@ -799,7 +799,7 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
#define H3_RST_BUS_UART2 51
#define H3_RST_BUS_UART3 52
-struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
+const struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
[H3_RST_USB_PHY0] = { 0x00cc, 0 },
[H3_RST_USB_PHY1] = { 0x00cc, 1 },
[H3_RST_USB_PHY2] = { 0x00cc, 2 },
@@ -830,7 +830,7 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[] = {
#define H3_R_RST_APB0_RSB 2
#define H3_R_RST_APB0_I2C 5
-struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = {
+const struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = {
[H3_R_RST_APB0_RSB] = { 0x00b0, 3 },
[H3_R_RST_APB0_I2C] = { 0x00b0, 6 },
};
@@ -853,7 +853,7 @@ struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = {
#define H6_RST_BUS_EHCI0 50
#define H6_RST_BUS_EHCI3 52
-struct sxiccmu_ccu_bit sun50i_h6_resets[] = {
+const struct sxiccmu_ccu_bit sun50i_h6_resets[] = {
[H6_RST_BUS_MMC0] = { 0x084c, 16 },
[H6_RST_BUS_MMC1] = { 0x084c, 17 },
[H6_RST_BUS_MMC2] = { 0x084c, 18 },
@@ -874,7 +874,7 @@ struct sxiccmu_ccu_bit sun50i_h6_resets[] = {
#define H6_R_RST_APB2_I2C 4
#define H6_R_RST_APB2_RSB 7
-struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
+const struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
[H6_R_RST_APB2_I2C] = { 0x019c, 16 },
[H6_R_RST_APB2_RSB] = { 0x01bc, 16 },
};
@@ -912,7 +912,7 @@ struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
#define R40_RST_BUS_UART6 79
#define R40_RST_BUS_UART7 80
-struct sxiccmu_ccu_bit sun8i_r40_resets[] = {
+const struct sxiccmu_ccu_bit sun8i_r40_resets[] = {
[R40_RST_USB_PHY0] = { 0x00cc, 0 },
[R40_RST_USB_PHY1] = { 0x00cc, 1 },
[R40_RST_USB_PHY2] = { 0x00cc, 2 },
@@ -961,7 +961,7 @@ struct sxiccmu_ccu_bit sun8i_r40_resets[] = {
#define V3S_RST_BUS_UART1 50
#define V3S_RST_BUS_UART2 51
-struct sxiccmu_ccu_bit sun8i_v3s_resets[] = {
+const struct sxiccmu_ccu_bit sun8i_v3s_resets[] = {
[V3S_RST_USB_PHY0] = { 0x00cc, 0 },
[V3S_RST_BUS_OHCI0] = { 0x02c0, 29 },
[V3S_RST_BUS_EHCI0] = { 0x02c0, 26 },
blob - a9a2cb503bec58ce7a90e383e64386b9e389a8a0
blob + 2e51b413e74a74428fd2b114489fe6eaf82fcc26
--- sys/dev/fdt/sxipio.c
+++ sys/dev/fdt/sxipio.c
@@ -69,7 +69,7 @@ struct sxipio_softc {
int sc_max_il;
int sc_min_il;
- struct sxipio_pin *sc_pins;
+ const struct sxipio_pin *sc_pins;
int sc_npins;
struct gpio_controller sc_gc;
@@ -125,11 +125,11 @@ void sxipio_a80_bias_cfg(struct sxipio_softc *, int,
u
struct sxipio_pins {
const char *compat;
- struct sxipio_pin *pins;
+ const struct sxipio_pin *pins;
int npins;
};
-struct sxipio_pins sxipio_pins[] = {
+const struct sxipio_pins sxipio_pins[] = {
{
"allwinner,sun4i-a10-pinctrl",
sun4i_a10_pins, nitems(sun4i_a10_pins)
blob - ac9677de3d1f3210c95b6ba3c0d805ad4a6c4345
blob + 7a3f81dea189fe9ef607aeac164721f8c29b8c75
--- sys/dev/fdt/sxipio_pins.h
+++ sys/dev/fdt/sxipio_pins.h
@@ -1,7 +1,7 @@
/* Public Domain */
-struct sxipio_pin sun4i_a10_pins[] = {
+const struct sxipio_pin sun4i_a10_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -1161,7 +1161,7 @@ struct sxipio_pin sun4i_a10_pins[] = {
} },
};
-struct sxipio_pin sun7i_a20_pins[] = {
+const struct sxipio_pin sun7i_a20_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -2340,7 +2340,7 @@ struct sxipio_pin sun7i_a20_pins[] = {
} },
};
-struct sxipio_pin sun8i_r40_pins[] = {
+const struct sxipio_pin sun8i_r40_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -3524,7 +3524,7 @@ struct sxipio_pin sun8i_r40_pins[] = {
} },
};
-struct sxipio_pin sun5i_a10s_pins[] = {
+const struct sxipio_pin sun5i_a10s_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -4277,7 +4277,7 @@ struct sxipio_pin sun5i_a10s_pins[] = {
} },
};
-struct sxipio_pin sun5i_a13_pins[] = {
+const struct sxipio_pin sun5i_a13_pins[] = {
{ SXIPIO_PIN(B, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -4743,7 +4743,7 @@ struct sxipio_pin sun5i_a13_pins[] = {
} },
};
-struct sxipio_pin sun5i_gr8_pins[] = {
+const struct sxipio_pin sun5i_gr8_pins[] = {
{ SXIPIO_PIN(B, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -5307,7 +5307,7 @@ struct sxipio_pin sun5i_gr8_pins[] = {
} },
};
-struct sxipio_pin sun8i_a33_pins[] = {
+const struct sxipio_pin sun8i_a33_pins[] = {
{ SXIPIO_PIN(B, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -5856,7 +5856,7 @@ struct sxipio_pin sun8i_a33_pins[] = {
} },
};
-struct sxipio_pin sun8i_h3_pins[] = {
+const struct sxipio_pin sun8i_h3_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -6412,7 +6412,7 @@ struct sxipio_pin sun8i_h3_pins[] = {
} },
};
-struct sxipio_pin sun8i_h3_r_pins[] = {
+const struct sxipio_pin sun8i_h3_r_pins[] = {
{ SXIPIO_PIN(L, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -6485,7 +6485,7 @@ struct sxipio_pin sun8i_h3_r_pins[] = {
} },
};
-struct sxipio_pin sun8i_v3s_pins[] = {
+const struct sxipio_pin sun8i_v3s_pins[] = {
{ SXIPIO_PIN(B, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -6802,7 +6802,7 @@ struct sxipio_pin sun8i_v3s_pins[] = {
} },
};
-struct sxipio_pin sun9i_a80_pins[] = {
+const struct sxipio_pin sun9i_a80_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -7615,7 +7615,7 @@ struct sxipio_pin sun9i_a80_pins[] = {
} },
};
-struct sxipio_pin sun9i_a80_r_pins[] = {
+const struct sxipio_pin sun9i_a80_r_pins[] = {
{ SXIPIO_PIN(L, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -7763,7 +7763,7 @@ struct sxipio_pin sun9i_a80_r_pins[] = {
} },
};
-struct sxipio_pin sun50i_a64_pins[] = {
+const struct sxipio_pin sun50i_a64_pins[] = {
{ SXIPIO_PIN(B, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -8414,7 +8414,7 @@ struct sxipio_pin sun50i_a64_pins[] = {
} },
};
-struct sxipio_pin sun50i_a64_r_pins[] = {
+const struct sxipio_pin sun50i_a64_r_pins[] = {
{ SXIPIO_PIN(L, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -8496,7 +8496,7 @@ struct sxipio_pin sun50i_a64_r_pins[] = {
} },
};
-struct sxipio_pin sun50i_h5_pins[] = {
+const struct sxipio_pin sun50i_h5_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
@@ -9092,7 +9092,7 @@ struct sxipio_pin sun50i_h5_pins[] = {
} },
};
-struct sxipio_pin sun50i_h6_pins[] = {
+const struct sxipio_pin sun50i_h6_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "emac", 2 },
} },
@@ -9764,7 +9764,7 @@ struct sxipio_pin sun50i_h6_pins[] = {
} },
};
-struct sxipio_pin sun50i_h6_r_pins[] = {
+const struct sxipio_pin sun50i_h6_r_pins[] = {
{ SXIPIO_PIN(L, 0), {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
blob - 28e611f595190ceebc7f7f218548dd2f533d0662
blob + e093b62f52146a8b4274809082935284df736b10
--- sys/dev/ic/imxiicvar.h
+++ sys/dev/ic/imxiicvar.h
@@ -38,7 +38,7 @@ struct imxiic_softc {
int sc_bitrate;
uint32_t sc_clkrate;
- struct imxiic_clk_pair *sc_clk_div;
+ const struct imxiic_clk_pair *sc_clk_div;
int sc_clk_ndiv;
struct rwlock sc_buslock;
@@ -61,7 +61,7 @@ struct imxiic_clk_pair {
uint16_t val;
};
-static struct imxiic_clk_pair imxiic_imx21_clk_div[50] = {
+static const struct imxiic_clk_pair imxiic_imx21_clk_div[50] = {
{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
@@ -77,7 +77,7 @@ static struct imxiic_clk_pair imxiic_imx21_clk_div[50]
{ 3072, 0x1E }, { 3840, 0x1F }
};
-static struct imxiic_clk_pair imxiic_vf610_clk_div[60] = {
+static const struct imxiic_clk_pair imxiic_vf610_clk_div[60] = {
{ 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
{ 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
{ 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
--
Christian "naddy" Weisgerber na...@mips.inka.de
