On Tue, May 17, 2022 at 07:20:49PM +0000, Miod Vallat wrote:
> As seen in sys/arch/powerpc64/include/trap.h, not-so-ancient PowerPC and
> POWER processors define exception addresses past EXC_LAST.
>
> The following diff changes EXC_LAST to no longer be the last
> "traditional" (0x100 bytes long) exception address, but the
> (conveniently page-aligned) end of the exception vectors area, and
> updates the pointer arithmetic accordingly.
>
> While there, this replaces a hardcoded number for the main Altivec
> exception with the proper symbolic constant (although the comment block
> following that ought to be updated).
>
> Tested on macppc, not tested on powerpc64 due to lack of hardware.
Both of your diffs passed a full regress run on powerpc64.
bluhm
> Index: sys/arch/macppc/macppc/machdep.c
> ===================================================================
> RCS file: /OpenBSD/src/sys/arch/macppc/macppc/machdep.c,v
> retrieving revision 1.195
> diff -u -p -r1.195 machdep.c
> --- sys/arch/macppc/macppc/machdep.c 7 Dec 2021 17:50:44 -0000 1.195
> +++ sys/arch/macppc/macppc/machdep.c 17 May 2022 14:56:04 -0000
> @@ -169,7 +169,7 @@ initppc(u_int startkernel, u_int endkern
> /*
> * Set up trap vectors
> */
> - for (exc = EXC_RSVD; exc <= EXC_LAST; exc += 0x100) {
> + for (exc = EXC_RSVD; exc < EXC_LAST; exc += 0x100) {
> switch (exc) {
> default:
> bcopy(&trapcode, (void *)exc, (size_t)&trapsize);
> @@ -212,7 +212,7 @@ initppc(u_int startkernel, u_int endkern
> }
>
> /* Grr, ALTIVEC_UNAVAIL is a vector not ~0xff aligned: 0x0f20 */
> - bcopy(&trapcode, (void *)0xf20, (size_t)&trapsize);
> + bcopy(&trapcode, (void *)EXC_VEC, (size_t)&trapsize);
>
> /*
> * since trapsize is > 0x20, we just overwrote the EXC_PERF handler
> @@ -222,7 +222,7 @@ initppc(u_int startkernel, u_int endkern
> * do not generate EXC_PERF exceptions...
> */
>
> - syncicache((void *)EXC_RST, EXC_LAST - EXC_RST + 0x100);
> + syncicache((void *)EXC_RST, EXC_LAST - EXC_RST);
>
> /*
> * Now enable translation (and machine checks/recoverable interrupts).
> Index: sys/arch/powerpc/include/trap.h
> ===================================================================
> RCS file: /OpenBSD/src/sys/arch/powerpc/include/trap.h,v
> retrieving revision 1.7
> diff -u -p -r1.7 trap.h
> --- sys/arch/powerpc/include/trap.h 26 Apr 2007 21:36:32 -0000 1.7
> +++ sys/arch/powerpc/include/trap.h 17 May 2022 14:56:04 -0000
> @@ -58,7 +58,8 @@
> #define EXC_DLMISS 0x1100 /* Data load translation miss */
> #define EXC_DSMISS 0x1200 /* Data store translation miss
> */
>
> -#define EXC_LAST 0x2f00 /* Last possible exception
> vector */
> +#define EXC_LAST 0x3000 /* End of last possible
> exception
> + vector */
>
> #define EXC_AST 0x3000 /* Fake AST vector */
>
> Index: sys/arch/powerpc64/include/trap.h
> ===================================================================
> RCS file: /OpenBSD/src/sys/arch/powerpc64/include/trap.h,v
> retrieving revision 1.8
> diff -u -p -r1.8 trap.h
> --- sys/arch/powerpc64/include/trap.h 11 Mar 2021 11:17:00 -0000 1.8
> +++ sys/arch/powerpc64/include/trap.h 17 May 2022 14:56:04 -0000
> @@ -1,3 +1,4 @@
> +/* $OpenBSD$ */
> /*-
> * SPDX-License-Identifier: BSD-4-Clause
> *
> @@ -105,7 +106,8 @@
> /* POWER8 */
> #define EXC_SOFT_PATCH 0x1500 /* POWER8 Soft Patch Exception
> */
>
> -#define EXC_LAST 0x2f00 /* Last possible exception
> vector */
> +#define EXC_LAST 0x3000 /* End of last possible
> exception
> + vector */
>
> #define EXC_AST 0x3000 /* Fake AST vector */
>
