On Wed, Jul 06, 2022 at 01:58:51PM -0700, Mike Larkin wrote: > On Wed, Jul 06, 2022 at 11:48:41AM -0500, Scott Cheloha wrote: > > > On Jul 6, 2022, at 11:36 AM, Mike Larkin <mlar...@nested.page> wrote: > > > > > > On Tue, Jul 05, 2022 at 07:16:26PM -0500, Scott Cheloha wrote: > > >> On Tue, Jul 05, 2022 at 01:38:32PM -0700, Mike Larkin wrote: > > >>> On Mon, Jul 04, 2022 at 09:06:55PM -0500, Scott Cheloha wrote: > > >>>> > > >>>> [...] > > >>> > > >>> Here's the output from a 4 socket 80 thread machine. > > >> > > >> Oh nice. I think this is the biggest machine we've tried so far. > > >> > > >>> kern.timecounter reports tsc after boot. > > >> > > >> Excellent. > > >> > > >>> Looks like this machine doesn't have the adjust MSR? > > >> > > >> IA32_TSC_ADJUST first appears in the Intel SDM Vol. 3 some time in > > >> 2011 or 2012. I can't find the exact revision. > > >> > > >> (I really wish there was a comprehensive version history for this sort > > >> of thing, i.e. this MSR first appeared in the blah-blah uarch, this > > >> instruction is available on all uarchs after yada-yada, etc.) > > >> > > >> There are apparently several versions of the E7-4870 in the E7 > > >> "family". If your CPU predates that, or launched 2012-2014, the MSR > > >> may not have made the cut. > > >> > > >> An aside: I cannot find any evidence of AMD supporting this MSR in any > > >> processor. It would be really, really nice if they did. If you (or > > >> anyone reading) knows anything about this, or whether they have an > > >> equivalent MSR, shout it out. > > >> > > >>> Other than that, machine seems stable. > > >> > > >> Good, glad to hear it. Thank you for testing. > > >> > > >> Has this machine had issues using the TSC on -current in the past? > > >> > > >> (If you have the time) what does the dmesg look like on the -current > > >> kernel with TSC_DEBUG enabled? > > > > > > Looks like you enabled TSC_DEBUG in your diff, so what I sent you is what > > > you > > > are asking for...? > > > > No, I mean on the -current *unpatched* kernel. Sorry if that wasn't > > clear. > > > > Our -current kernel prints more detailed information if TSC_DEBUG > > is enabled. In particular, I'm curious if the unpatched kernel > > detects any skew or drift on your machine, and if so, how much. > > > > here you go. I didnt run with all 80 cpus since -current doesnt have my > " > 64 cpus" diff, but I think this is what you're after in any case.
Yes! This is what I was looking for, thanks. > cpu0: TSC skew=0 observed drift=0 > cpu1: TSC skew=112 observed drift=0 > cpu2: TSC skew=102 observed drift=0 > cpu3: TSC skew=-134 observed drift=0 > cpu4: TSC skew=4 observed drift=0 > cpu5: TSC skew=68 observed drift=0 > cpu6: TSC skew=22 observed drift=0 > cpu7: TSC skew=-52 observed drift=0 > cpu8: TSC skew=8 observed drift=0 > cpu9: TSC skew=-18 observed drift=0 > cpu10: TSC skew=10 observed drift=0 > cpu11: TSC skew=76 observed drift=0 > cpu12: TSC skew=-2 observed drift=0 > cpu13: TSC skew=-4 observed drift=0 > cpu14: TSC skew=-2 observed drift=0 > cpu15: TSC skew=-28 observed drift=0 > cpu16: TSC skew=6 observed drift=0 > cpu17: TSC skew=-8 observed drift=0 > cpu18: TSC skew=0 observed drift=0 > cpu19: TSC skew=-32 observed drift=0 > cpu20: TSC skew=0 observed drift=0 > cpu21: TSC skew=-26 observed drift=0 > cpu22: TSC skew=0 observed drift=0 > cpu23: TSC skew=22 observed drift=0 > cpu24: TSC skew=-12 observed drift=0 > cpu25: TSC skew=-14 observed drift=0 > cpu26: TSC skew=76 observed drift=0 > cpu27: TSC skew=-64 observed drift=0 > cpu28: TSC skew=-2 observed drift=0 > cpu29: TSC skew=34 observed drift=0 > cpu30: TSC skew=22 observed drift=0 > cpu31: TSC skew=-58 observed drift=0 > cpu32: TSC skew=-2 observed drift=0 > cpu33: TSC skew=6 observed drift=0 > cpu34: TSC skew=46 observed drift=0 > cpu35: TSC skew=20 observed drift=0 > cpu36: TSC skew=34 observed drift=0 > cpu37: TSC skew=-8 observed drift=0 > cpu38: TSC skew=48 observed drift=0 > cpu39: TSC skew=-10 observed drift=0 > cpu40: TSC skew=0 observed drift=0 > cpu41: TSC skew=72 observed drift=0 > cpu42: TSC skew=2 observed drift=0 > cpu43: TSC skew=-46 observed drift=0 > cpu44: TSC skew=-2 observed drift=0 > cpu45: TSC skew=-14 observed drift=0 > cpu46: TSC skew=-2 observed drift=0 > cpu47: TSC skew=-32 observed drift=0 > cpu48: TSC skew=12 observed drift=0 > cpu49: TSC skew=-16 observed drift=0 > cpu50: TSC skew=84 observed drift=0 > cpu51: TSC skew=-44 observed drift=0 > cpu52: TSC skew=-4 observed drift=0 > cpu53: TSC skew=4 observed drift=0 > cpu54: TSC skew=16 observed drift=0 > cpu55: TSC skew=-56 observed drift=0 > cpu56: TSC skew=-10 observed drift=0 > cpu57: TSC skew=6 observed drift=0 > cpu58: TSC skew=6 observed drift=0 > cpu59: TSC skew=-40 observed drift=0 > cpu60: TSC skew=-4 observed drift=0 > cpu61: TSC skew=-6 observed drift=0 > cpu62: TSC skew=74 observed drift=0 > cpu63: TSC skew=-48 observed drift=0
