This patch switches loongson and octeon to clockintr(9).
It has survived several release builds and upgrades from the resulting
bsd.rd images on my ER-4. The ER-4 doesn't have enough RAM to crunch a
parallel release build. It chokes on some of the larger LLVM modules.
visa@ reports it survived a partial build on a loongson machine (he
skipped LLVM). I believe he is also testing this on a package
building machine, too.
Testing on beefier octeon machines would help demonstrate this is
stable. My ER-4 only has USB2.0, which slows things down.
Notes:
- octeon and loongson machines now have a randomized statclock().
- This patch merely disables the loongson glxclk. If the device has
no other use we can fully remove the driver in a separate patch.
Index: sys/arch/mips64/include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/mips64/include/cpu.h,v
retrieving revision 1.139
diff -u -p -r1.139 cpu.h
--- sys/arch/mips64/include/cpu.h 22 Aug 2022 00:35:06 -0000 1.139
+++ sys/arch/mips64/include/cpu.h 6 Nov 2022 19:09:21 -0000
@@ -106,6 +106,7 @@
#if defined(_KERNEL) && !defined(_LOCORE)
+#include <sys/clockintr.h>
#include <sys/device.h>
#include <machine/intr.h>
#include <sys/sched.h>
@@ -179,8 +180,8 @@ struct cpu_info {
uint32_t ci_softpending; /* pending soft interrupts */
int ci_clock_started;
volatile int ci_clock_deferred; /* clock interrupt postponed */
- u_int32_t ci_cpu_counter_last; /* last compare value loaded */
- u_int32_t ci_cpu_counter_interval; /* # of counter ticks/tick */
+ struct clockintr_queue
+ ci_queue;
struct pmap *ci_curpmap;
uint ci_intrdepth; /* interrupt depth */
Index: sys/arch/mips64/include/_types.h
===================================================================
RCS file: /cvs/src/sys/arch/mips64/include/_types.h,v
retrieving revision 1.23
diff -u -p -r1.23 _types.h
--- sys/arch/mips64/include/_types.h 5 Mar 2018 01:15:25 -0000 1.23
+++ sys/arch/mips64/include/_types.h 6 Nov 2022 19:09:21 -0000
@@ -35,6 +35,8 @@
#ifndef _MIPS64__TYPES_H_
#define _MIPS64__TYPES_H_
+#define __HAVE_CLOCKINTR
+
/*
* _ALIGN(p) rounds p (pointer or byte index) up to a correctly-aligned
* value for all data types (int, long, ...). The result is an
Index: sys/arch/mips64/mips64/clock.c
===================================================================
RCS file: /cvs/src/sys/arch/mips64/mips64/clock.c,v
retrieving revision 1.47
diff -u -p -r1.47 clock.c
--- sys/arch/mips64/mips64/clock.c 31 Oct 2022 13:59:10 -0000 1.47
+++ sys/arch/mips64/mips64/clock.c 6 Nov 2022 19:09:21 -0000
@@ -38,8 +38,10 @@
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/atomic.h>
+#include <sys/clockintr.h>
#include <sys/device.h>
#include <sys/evcount.h>
+#include <sys/stdint.h>
#include <machine/autoconf.h>
#include <machine/cpu.h>
@@ -47,6 +49,8 @@
static struct evcount cp0_clock_count;
static int cp0_clock_irq = 5;
+uint64_t cp0_nsec_cycle_ratio;
+uint64_t cp0_nsec_max;
int clockmatch(struct device *, void *, void *);
void clockattach(struct device *, struct device *, void *);
@@ -59,9 +63,18 @@ const struct cfattach clock_ca = {
sizeof(struct device), clockmatch, clockattach
};
-void cp0_startclock(struct cpu_info *);
-void cp0_trigger_int5(void);
+void cp0_rearm_int5(void *, uint64_t);
+void cp0_trigger_int5_wrapper(void *);
+
+const struct intrclock cp0_intrclock = {
+ .ic_rearm = cp0_rearm_int5,
+ .ic_trigger = cp0_trigger_int5_wrapper
+};
+
uint32_t cp0_int5(uint32_t, struct trapframe *);
+void cp0_startclock(struct cpu_info *);
+void cp0_trigger_int5(void);
+void cp0_trigger_int5_masked(void);
int
clockmatch(struct device *parent, void *vcf, void *aux)
@@ -74,8 +87,13 @@ clockmatch(struct device *parent, void *
void
clockattach(struct device *parent, struct device *self, void *aux)
{
+ uint64_t cp0_freq = curcpu()->ci_hw.clock / CP0_CYCLE_DIVIDER;
+
printf(": int 5\n");
+ cp0_nsec_cycle_ratio = cp0_freq * (1ULL << 32) / 1000000000;
+ cp0_nsec_max = UINT64_MAX / cp0_nsec_cycle_ratio;
+
/*
* We need to register the interrupt now, for idle_mask to
* be computed correctly.
@@ -100,20 +118,19 @@ clockattach(struct device *parent, struc
uint32_t
cp0_int5(uint32_t mask, struct trapframe *tf)
{
- u_int32_t clkdiff, pendingticks = 0;
struct cpu_info *ci = curcpu();
int s;
+ atomic_inc_long((unsigned long *)&cp0_clock_count.ec_count);
+
+ cp0_set_compare(cp0_get_count() - 1); /* clear INT5 */
+
/*
- * If we got an interrupt before we got ready to process it,
- * retrigger it as far as possible. cpu_initclocks() will
- * take care of retriggering it correctly.
+ * Just ignore the interrupt if we're not ready to process it.
+ * cpu_initclocks() will retrigger it later.
*/
- if (ci->ci_clock_started == 0) {
- cp0_set_compare(cp0_get_count() - 1);
-
+ if (!ci->ci_clock_started)
return CR_INT_5;
- }
/*
* If the clock interrupt is logically masked, defer all
@@ -121,36 +138,11 @@ cp0_int5(uint32_t mask, struct trapframe
*/
if (tf->ipl >= IPL_CLOCK) {
ci->ci_clock_deferred = 1;
- cp0_set_compare(cp0_get_count() - 1);
return CR_INT_5;
}
ci->ci_clock_deferred = 0;
/*
- * Count how many ticks have passed since the last clock interrupt...
- */
- clkdiff = cp0_get_count() - ci->ci_cpu_counter_last;
- while (clkdiff >= ci->ci_cpu_counter_interval) {
- ci->ci_cpu_counter_last += ci->ci_cpu_counter_interval;
- clkdiff = cp0_get_count() - ci->ci_cpu_counter_last;
- pendingticks++;
- }
- pendingticks++;
- ci->ci_cpu_counter_last += ci->ci_cpu_counter_interval;
-
- /*
- * Set up next tick, and check if it has just been hit; in this
- * case count it and schedule one tick ahead.
- */
- cp0_set_compare(ci->ci_cpu_counter_last);
- clkdiff = cp0_get_count() - ci->ci_cpu_counter_last;
- if ((int)clkdiff >= 0) {
- ci->ci_cpu_counter_last += ci->ci_cpu_counter_interval;
- pendingticks++;
- cp0_set_compare(ci->ci_cpu_counter_last);
- }
-
- /*
* Process clock interrupt.
*/
s = splclock();
@@ -160,22 +152,65 @@ cp0_int5(uint32_t mask, struct trapframe
sr = getsr();
ENABLEIPI();
#endif
- while (pendingticks) {
- atomic_inc_long((unsigned long *)&cp0_clock_count.ec_count);
- hardclock(tf);
- pendingticks--;
- }
+ clockintr_dispatch(tf);
#ifdef MULTIPROCESSOR
setsr(sr);
#endif
ci->ci_ipl = s;
-
return CR_INT_5; /* Clock is always on 5 */
}
/*
- * Trigger the clock interrupt.
- *
+ * Arm INT5 to fire after the given number of nanoseconds have elapsed.
+ * Only try once. If we miss, let cp0_trigger_int5_masked() handle it.
+ */
+void
+cp0_rearm_int5(void *unused, uint64_t nsecs)
+{
+ uint32_t cycles, t0, t1, target;
+ register_t sr;
+
+ if (nsecs > cp0_nsec_max)
+ nsecs = cp0_nsec_max;
+ cycles = (nsecs * cp0_nsec_cycle_ratio) >> 32;
+
+ /*
+ * Set compare, then immediately reread count. If INT5 is not
+ * pending then we need to check if we missed. If t0 + cycles
+ * did not overflow then we need t0 <= t1 < target. Otherwise,
+ * there are two valid constraints: either t0 <= t1 or t1 < target
+ * show we didn't miss.
+ */
+ sr = disableintr();
+ t0 = cp0_get_count();
+ target = t0 + cycles;
+ cp0_set_compare(target);
+ t1 = cp0_get_count();
+ if (!ISSET(cp0_get_cause(), CR_INT_5)) {
+ if (t0 <= target) {
+ if (target <= t1 || t1 < t0)
+ cp0_trigger_int5_masked();
+ } else {
+ if (t1 < t0 && target <= t1)
+ cp0_trigger_int5_masked();
+ }
+ }
+ setsr(sr);
+}
+
+void
+cp0_trigger_int5(void)
+{
+ register_t sr;
+
+ sr = disableintr();
+ cp0_trigger_int5_masked();
+ setsr(sr);
+}
+
+/*
+ * Arm INT5 to fire as soon as possible.
+ *
* We need to spin until either (a) INT5 is pending or (b) the compare
* register leads the count register, i.e. we know INT5 will be pending
* very soon.
@@ -187,25 +222,27 @@ cp0_int5(uint32_t mask, struct trapframe
* to arm the timer on most Octeon hardware.
*/
void
-cp0_trigger_int5(void)
+cp0_trigger_int5_masked(void)
{
uint32_t compare, offset = 16;
int leading = 0;
- register_t sr;
- sr = disableintr();
- while (!leading && !ISSET(cp0_get_cause(), CR_INT_5)) {
+ while (!ISSET(cp0_get_cause(), CR_INT_5) && !leading) {
compare = cp0_get_count() + offset;
cp0_set_compare(compare);
leading = (int32_t)(compare - cp0_get_count()) > 0;
offset *= 2;
}
- setsr(sr);
+}
+
+void
+cp0_trigger_int5_wrapper(void *unused)
+{
+ cp0_trigger_int5();
}
/*
- * Start the real-time and statistics clocks. Leave stathz 0 since there
- * are no other timers available.
+ * Start the clock interrupt dispatch cycle.
*/
void
cp0_startclock(struct cpu_info *ci)
@@ -225,12 +262,11 @@ cp0_startclock(struct cpu_info *ci)
}
#endif
+ clockintr_cpu_init(&cp0_intrclock);
+
/* Start the clock. */
s = splclock();
- ci->ci_cpu_counter_interval =
- (ci->ci_hw.clock / CP0_CYCLE_DIVIDER) / hz;
- ci->ci_cpu_counter_last = cp0_get_count() + ci->ci_cpu_counter_interval;
- cp0_set_compare(ci->ci_cpu_counter_last);
- ci->ci_clock_started++;
+ ci->ci_clock_started = 1;
+ clockintr_trigger();
splx(s);
}
Index: sys/arch/mips64/mips64/mips64_machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/mips64/mips64/mips64_machdep.c,v
retrieving revision 1.39
diff -u -p -r1.39 mips64_machdep.c
--- sys/arch/mips64/mips64/mips64_machdep.c 30 Oct 2022 17:43:39 -0000
1.39
+++ sys/arch/mips64/mips64/mips64_machdep.c 6 Nov 2022 19:09:21 -0000
@@ -44,6 +44,7 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
+#include <sys/clockintr.h>
#include <sys/proc.h>
#include <sys/exec.h>
#include <sys/sysctl.h>
@@ -302,16 +303,15 @@ cp0_calibrate(struct cpu_info *ci)
}
/*
- * Start the real-time and statistics clocks.
+ * Prepare to start the clock interrupt dispatch cycle.
*/
void
cpu_initclocks(void)
{
struct cpu_info *ci = curcpu();
- profhz = hz;
-
tick = 1000000 / hz; /* number of micro-seconds between interrupts */
+ tick_nsec = 1000000000 / hz;
cp0_calibrate(ci);
@@ -324,6 +324,10 @@ cpu_initclocks(void)
tc_init(&cp0_timecounter);
}
+ stathz = hz;
+ profhz = stathz * 10;
+ clockintr_init(CL_RNDSTAT);
+
#ifdef DIAGNOSTIC
if (md_startclock == NULL)
panic("no clock");
@@ -331,14 +335,10 @@ cpu_initclocks(void)
(*md_startclock)(ci);
}
-/*
- * We assume newhz is either stathz or profhz, and that neither will
- * change after being set up above. Could recalculate intervals here
- * but that would be a drag.
- */
void
setstatclockrate(int newhz)
{
+ clockintr_setstatclockrate(newhz);
}
/*
Index: sys/arch/loongson/dev/apm.c
===================================================================
RCS file: /cvs/src/sys/arch/loongson/dev/apm.c,v
retrieving revision 1.40
diff -u -p -r1.40 apm.c
--- sys/arch/loongson/dev/apm.c 6 Apr 2022 18:59:26 -0000 1.40
+++ sys/arch/loongson/dev/apm.c 6 Nov 2022 19:09:21 -0000
@@ -38,6 +38,7 @@
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/proc.h>
+#include <sys/clockintr.h>
#include <sys/device.h>
#include <sys/fcntl.h>
#include <sys/ioctl.h>
@@ -415,7 +416,13 @@ apm_suspend(int state)
if (rv == 0)
rv = sys_platform->resume();
}
+
inittodr(gettime()); /* Move the clock forward */
+#ifdef __HAVE_CLOCKINTR
+ clockintr_cpu_init(NULL);
+ clockintr_trigger();
+#endif
+
config_suspend_all(DVACT_RESUME);
cold = 0;
Index: sys/arch/loongson/dev/glxclk.c
===================================================================
RCS file: /cvs/src/sys/arch/loongson/dev/glxclk.c,v
retrieving revision 1.7
diff -u -p -r1.7 glxclk.c
--- sys/arch/loongson/dev/glxclk.c 18 Aug 2022 06:31:36 -0000 1.7
+++ sys/arch/loongson/dev/glxclk.c 6 Nov 2022 19:09:21 -0000
@@ -114,6 +114,9 @@ glxclk_attach(struct device *parent, str
u_int64_t wa;
int statint, minint;
+ printf(" not configured\n");
+ return;
+
glxclk_sc->sc_iot = gaa->gaa_iot;
glxclk_sc->sc_ioh = gaa->gaa_ioh;
