from: https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/System-registers/The-system-control-register?lang=en
The following patch tries to describe the system register in the source code to the best of my ability. Source comment change only, no binary change. Excuse that this is against a patched 7.2 system, please. If you would like to ask me a question regarding this patch reply to me directly as I'm not on the tech@ list. -peter Index: armreg.h =================================================================== RCS file: /cvs/src/sys/arch/arm64/include/armreg.h,v retrieving revision 1.21 diff -u -p -u -r1.21 armreg.h --- armreg.h 29 Aug 2022 02:01:18 -0000 1.21 +++ armreg.h 29 Dec 2022 12:48:23 -0000 @@ -560,26 +560,26 @@ #define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */ #define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */ -#define SCTLR_M 0x0000000000000001 -#define SCTLR_A 0x0000000000000002 -#define SCTLR_C 0x0000000000000004 -#define SCTLR_SA 0x0000000000000008 -#define SCTLR_SA0 0x0000000000000010 -#define SCTLR_CP15BEN 0x0000000000000020 -#define SCTLR_THEE 0x0000000000000040 -#define SCTLR_ITD 0x0000000000000080 -#define SCTLR_SED 0x0000000000000100 -#define SCTLR_UMA 0x0000000000000200 -#define SCTLR_I 0x0000000000001000 -#define SCTLR_DZE 0x0000000000004000 -#define SCTLR_UCT 0x0000000000008000 -#define SCTLR_nTWI 0x0000000000010000 -#define SCTLR_nTWE 0x0000000000040000 -#define SCTLR_WXN 0x0000000000080000 -#define SCTLR_SPAN 0x0000000000800000 -#define SCTLR_EOE 0x0000000001000000 -#define SCTLR_EE 0x0000000002000000 -#define SCTLR_UCI 0x0000000004000000 +#define SCTLR_M 0x0000000000000001 /* enable MMU */ +#define SCTLR_A 0x0000000000000002 /* alignment check enable bit */ +#define SCTLR_C 0x0000000000000004 /* data cache enable */ +#define SCTLR_SA 0x0000000000000008 /* stack alignment check enbl */ +#define SCTLR_SA0 0x0000000000000010 /* stack align check for sa0 */ +#define SCTLR_CP15BEN 0x0000000000000020 /* CP15 barrier enable */ +#define SCTLR_THEE 0x0000000000000040 +#define SCTLR_ITD 0x0000000000000080 /* IT disable */ +#define SCTLR_SED 0x0000000000000100 /* SET END disable */ +#define SCTLR_UMA 0x0000000000000200 /* User Mask access */ +#define SCTLR_I 0x0000000000001000 /* Instruction cache enable */ +#define SCTLR_DZE 0x0000000000004000 /* access to DC ZVA Instr. */ +#define SCTLR_UCT 0x0000000000008000 /* Enable El0 access */ +#define SCTLR_nTWI 0x0000000000010000 /* Not trap WFI */ +#define SCTLR_nTWE 0x0000000000040000 /* Not trap WFE */ +#define SCTLR_WXN 0x0000000000080000 /* write perm implies XN */ +#define SCTLR_SPAN 0x0000000000800000 +#define SCTLR_EOE 0x0000000001000000 /* endianness of explcit data */ +#define SCTLR_EE 0x0000000002000000 /* exception endianness */ +#define SCTLR_UCI 0x0000000004000000 /* enable 64-bit ELO access */ /* SPSR_EL1 */ /*
