On 09/13/08 19:22, Dana H. Myers wrote:
> Bill Holler wrote:
>
>> Changing the HPET interrupt to Level triggered added about
>> 2 micro seconds to the ISR compared with using Edge triggered.
>> The ISR must now verify an interrupt is pending and tell the
>> HPET its interrupt was serviced with a read and a write of HPET
>> registers.
>>
>> The apic code looks like it will not allow sharing of Edge
>> triggered I/O APIC interrupts? Perhaps we should keep
>> using an Edge triggered HPET interrupt instead of Level
>> triggered?
>>
>>
> You can't share edge-triggered interrupts reliably, really.
>
Yes.
My question is "will apic_setup_irq_table() prevent sharing
edge-triggered interrupts?"
We use this apic_setup_irq_table() call:
if (apic_setup_irq_table(NULL, apic_hpet_vect, NULL,
&ispec, &apic_hpet_flags, DDI_INTR_TYPE_FIXED) < 0) {
cmn_err(CE_WARN, "!apic: HPET setup failed");
return;
}
apic_setup_irq_table() will use this clause:
} else if (intr_flagp != NULL) {
I did not see where apic_irq_table[irqno]->airq_mps_intr_index
is set to ACPI_INDEX? Is this only for the SCI interrupt?
Otherwise apic_setup_irq_table() calls:
} else if ((vector = apic_allocate_vector(ipl, irqno, 0)) == 0) {
if ((newirq = apic_share_vector(irqno, intr_flagp,
intr_index,
ipl, ioapicindex, ipin, &irqptr)) != -1) {
It looks like apic_allocate_vector() will only allocate free vectors?
apic_share_vector() will check the airq_rdt_entry's match in
these bits 0xFF00. This verifies the interrupts are both LEVEL
or both EDGE.
As far as I can tell the interface we use to allocate the interrupt
will not share a LEVEL and EDGE interrupt. If this is true we can
use an edge-triggered interrupt knowing Solaris will not share the irq.
Is this true?
Thank you!
Bill
> Dana
>
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