Hi Aubrey, Li, Aubrey wrote: > Hi Eric, > > When processor group is initialized, the group position in the > cmt_pgs->grp_set[index] is determined. For example, on my platform, > the current implementation is: > > PGHW_POW_IDLE @ level = 0 > PGHW_POW_ACTIVE @ level = 1 > PGHW_CHIP @ level = 2 > PGHW_CACHE @ level = 3 > PGHW_IPIPE @ level = 4 > > And I found when cmt_balance searches the target processor group, > it returns CPU in the first available group. > Right. The routine work by balancing from the top down. It must correct an imbalance at a higher level before moving to a lower level, and it can only do this one level at a time, since the load from a correction at one level must be realized before moving lower.
> Does this mean sometimes dispatcher uses CMT_COALESCE in power idle > group, and sometimes dispatcher uses CMT_BALANCE in the processor group > among which CPUs share the last level cache? > Because it works top down, in this case, the coalescence policy will be implemented until there's nothing more to do at that level, before moving lower. This is the first time we've allowed different policies to be implemented across the hierarchy, so i'm really happy you are taking a look at this. I haven't looked at it closely yet since I've still been focused on getting the nuts and bolts of the dispatcher driven p-state changes to happen... :) -Eric
