http://defect.opensolaris.org/bz/show_bug.cgi?id=3097
Summary: Remove cli requirement from idle threads and HPET ISR
Classification: Development
Product: power-mgmt
Version: unspecified
Platform: i86pc/amd64
OS/Version: Solaris
Status: NEW
Severity: major
Priority: P2
Component: c-state
AssignedTo: bill.holler at sun.com
ReportedBy: bill.holler at sun.com
CC: tesla-dev at opensolaris.org
Estimated Hours: 0.0
The current implementation blocks interrupts during CPUs idle setup.
The HPET interrupt service routine must also block interrupts to
avoid an interrupt blocking with an idle thread while they attempt
to acquire the HPET mutex.
Blocking interrupts was implemented for testing on legacy processors
with variant TSC in deep C-States. The TSC had to be re-synched before
servicing interrupts. This requirement does not exist on supported
processors with deep C-State invariant TSC.
Some code assumes it can poke around in a CPU's cyclic data structures
without locks because it is running from the idle thread with interrupts
disabled. Changing a CPU's cyclic data structures is only ever done
by a thread executing on that CPU; this cannot happen when interrupts
are blocked. This cyclic code needs to be looked at to see what needs
to be done with respect to now running with interrupts enabled.
It is possible to get the next cyclic fire by reading the local APIC
timer directly instead of accessing the cy_expire field of the cyclic_t
on top of the CPU's cyclic heap.
Leaving interrupts enabled will also allow interrupts to run at
placed in the idle loop where it was assumed they could not.
Setup and cleanup code in acpi_cpu_cstate() needs to be looked at
for correctness with interrupts enabled.It will now be possible for
interrupts to add latency between the check for the next cyclic expire
and scheduling this on the HPET. The HPET scheduling code should already
be able to handle this; it currently returns a status code for programming
HPET success.
Lost wakeups need to be avoided. Perhaps the HPET scheduling code
will need to disable interrupts before programming the HPET for this
CPU and return with interrupts disabled.
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