Eric Saxe wrote: > > Yea, it's a good question. My impression of the T-states, is that in the > general (common) case the system wouldn't use them, since from my > understanding their purpose is mainly as a mechanism for quickly (and > forcibly) throttling the processor clock to bring a thermal situation > under control. Let's think about that. T-states represent nothing more than the ability to hold the CPU for some percentage of clock cycles. T-states do not reduce the CPU clock and do not reduce the voltage to the CPU.
Given a choice between a T-state that halts the CPU for 50% of the clock cycles and a P-state which runs the CPU at 50% of full-speed, the P-state will win in terms of power savings (and thermal safety) every time. Given that the thermal time-constant of a CPU is *much* greater than the time it takes to switch P-states, I don't think there's a compelling case for T-state usage *when P-states are supported*. T-states give a linear power reduction, while P-states give a geometric power reduction. While T-state switching is of much lower latency, it is no more forcible than switch P-states. Where I can see T-states being useful is on systems where there's no P-state support, or to create intermediate levels between P-states. > It's also my understanding that the performance impact of > the T-states are fairly severe, which begs the question if we would ever > want the CPU to enter them when not idle. When the CPU is idle, I would > wonder how T-states would compare to what we get from entering the C1 > state. Since T-states don't change the voltage, I would guess that C1 > would actually buy more. Maybe Aubrey or someone else can correct me if > I'm mistaken... I don't believe it makes sense to compare T-states to C-states - I'd compare T-states to P-states. The performance impact of a T-state is comparable to that of a P-state which runs at the same effective clock rate, while the power savings of a P-state is greater. > > Aren't there also cases where the processor could go into a T-state > without the OS actually knowing? It's certainly possible that the chipset could start holding the CPU halted for some percentage of clock cycles, I suppose. Dana
